MPC875 datasheet(14/84 Pages) FREESCALE

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MPC875/MPC870 Hardware Specifications, Rev. 3.0

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

Freescale Semiconductor

Mandatory Reset Configurations

Figure 3. Example Voltage Sequencing Circuit

Mandatory Reset Configurations

The MPC875/870 requires a mandatory configuration during reset.

If hardware reset configuration word (HRCW) is enabled, the HRCW[DBGC] value needs to be set to binary X1 in

the HRCW and the SIUMCR[DBGC] should be programmed with the same value in the boot code after reset. This

can be done by asserting the RSTCONF during HRESET assertion.

If HRCW is disabled, the SIUMCR[DBGC] should be programmed with binary X1 in the boot code after reset by

negating the RSTCONF during the HRESET assertion.

The MBMR[GPLB4DIS], PAPAR, PADIR, PBPAR, PBDIR, PCPAR, and PCDIR need to be configured with the

mandatory values in Table 7 in the boot code after the reset is negated.

Table 7. Mandatory Reset Configuration of MPC875/870

Field

Value

(binary)

HRCW

(Hardware reset configuration word)

HRCW[DBGC]

SIUMCR

(SIU module configuration register)

SIUMCR[DBGC]

MBMR

(Machine B mode register)

MBMR[GPLB4DIS}

PAPAR

(Port A pin assignment register)

PAPAR[5:9]

PAPAR[12:13]

PADIR

(Port A data direction register)

PADIR[5:9]

PADIR[12:13]

PBPAR

(Port B pin assignment register)

PBPAR[14:18]

PBPAR[20:22]

PBDIR

(Port B data direction register)

PBDIR[14:8]

PBDIR[20:22]

PCPAR

(Port C pin assignment register)

PCPAR[4:5]

PCPAR[8:9]

PCPAR[14]

VDDH

VDDL

1N5820

MUR420

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