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MPC875 数据表(PDF) 24 Page - Freescale Semiconductor, Inc |
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MPC875 数据表(HTML) 24 Page - Freescale Semiconductor, Inc |
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24 / 84 page ![]() MPC875/MPC870 Hardware Specifications, Rev. 3.0 24 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor Bus Signal Timing Figure 4 provides the control timing diagram. . Figure 4. Control Timing Figure 5 provides the timing for the external clock. Figure 5. External Clock Timing CLKOUT Outputs A B 2.0 V 0.8 V 0.8 V 2.0 V 2.0 V 0.8 V 2.0 V 0.8 V Outputs 2.0 V 0.8 V 2.0 V 0.8 V B A Inputs 2.0 V 0.8 V 2.0 V 0.8 V D C Inputs 2.0 V 0.8 V 2.0 V 0.8 V C D A Maximum output delay specification B Minimum output hold time C Minimum input setup time specification D Minimum input hold time specification CLKOUT B1 B5 B3 B4 B1 B2 |
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