DP5380 datasheet(3/32 Pages) NSC

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10 Functional Description (Continued)

12 mP INTERFACE

Figure 2 shows a block diagram of the ASI Key blocks with-

in the ASI are ReadWrite registers with associated decode

and control logic interrupt and DMA logic SCSI bus arbitra-

tion logic SCSI driversreceivers with parity and the SCSI

data input and output registers The ASI has three interfac-

es one to SCSI one to a DMA controller and the third to a

P The internal registers control all operations of the ASI

The mP interface consists of non-multiplexed address and

data busses with associated control signals Address de-

code logic selects a register for reading or writing The ad-

dress lines A0 – 2 select the register for mP accesses while

for DMA accesses the address lines are ignored

The register bank consists of twelve registers mapped into

an address space of eight locations Upon an external chip

reset the registers are cleared (all zeroes)

13 DMA INTERFACE

The DMA logic interfaces to single-cycle block mode flow-

through or fly-by controllers Single byte transfers are ac-

complished via the DRQDACK handshake signals Block

mode transfers use the READY output to control the speed

(insert wait-states) An End Of Process (EOP) input from the

DMA controller signals the ASI to halt DMA transfers An

interrupt can be generated for DMA completion or an error

(see Section 50) All DMA data passes through the SCSI

data input and output registers automatically selected dur-

ing DMA cycles

14 SCSI INTERFACE

The ASI contains all logic required to interface directly to the

SCSI bus Direct control and monitoring of all SCSI signals

is provided The state of each SCSI signal may be deter-

mined by reading a register which continuously reflects the

state of the bus Each signal may be asserted by writing a

ONE to the appropriate bit

The ASI includes logic to automatically handle SCSI timing

sequences too fast for mP control In particular there is

hardware support for DMA transfers bus arbitration selec-

tionreselection bus phase monitoring BSY monitoring for

bus disconnection bus reset and parity generation and

checking

TLF9756 – 3

FIGURE 2 ASI Block Diagram

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