DP5380 datasheet(12/32 Pages) NSC

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40 Device Operation (Continued)

Target Send

*DATA IN PHASE*

Program DMA Controller

TCR

4 01h

*phase*

ICR

4 09h

MR2

4 4Ah

SDS

4 0

*Start DMA Send*

while (NOT interrupt)

idle

if(NOT(BSREnd of DMA)

error

else

*DMA end*

repeat

while (CSBREQ OR BSRACK)

loop count

4 3

loop count

*decrement*

until (loop count

44 0)

MR2

4 40h

Change phase as required

Some explanation of the final part of Target Send is re-

quired In this type of DMA operation it is very difficult to

exactly determine the True End of DMA simply detecting

REQ and ACK simultaneously inactive is not enough

Reference to

Figure 482 will help to understand the follow-

ing text

TLF9756 – 8

FIGURE 482 Target Send DMA

As shown in

Figure 482 ACK going active causes the DRQ

for the next byte and also REQ to go inactive ACK going

inactive allows REQ to go active for the next byte If the

INITIATOR is slow removing ACK the mP may sample the

SCSI bus after the EOP interrupt at point A Here both REQ

and ACK will be inactive but there is one more byte to

transfer on SCSI Due to chip timing delays this condition

will not last more than 200 ns A safe way to determine the

True End of DMA is to sample REQ and ACK and ONLY

when both are inactive in three successive samples will the

P be at point B in the figure

49 BLOCK MODE DMA TRANSFERS

In Block Mode the DMA interface uses the DRQ DACK

EOP and READY lines DRQ is asserted once at the begin-

ning of transfers and deasserted once DACK is received

DACK should be asserted continuously for the duration of

all the transfer EOP should be asserted during the last

DMA byte signal when the next DMA byte transfers The

ASI asserts the READY signal when the next DMA byte

should be transferred

As for non-block mode the End of DMA interrupt is just

EOP also in block mode receive the ASI does not return

READY to an active signal after EOP This means external

logic must gate off READY if the mP is not to be locked up

For more details see Section 70

The block mode is intended for systems where the over-

head of handing the system busses to and from the mP and

DMA controller is too great The block mode handshake is

not necessarily faster than non-block (it may be) but the

overall transfer rate is improved once the bus exchange

overhead is removed Of course the mP is prevented from

executing for the whole DMA operation

If a phase mismatch occurs the READY signal is left in the

inactive state The DMA controller must hand back the bus

to the mP and the inactive READY signal may need to be

gated off

When performing DMA as an INITIATOR the EOP signal

does not deassert ACK on the SCSI bus Firmware must

determine when REQ is inactive after the last SCSI transfer

then reset the MR2 DMA bit to deassert ACK

Programming the ASI in block mode is the same as non-

block mode except bit 7 in MR2 should also be set

410 PSEUDO DMA

The system design can utilize ASI DMA logic for non-data

transfers This removes the need to poll REQ ACK and pro-

gram the assertiondeassertion of the handshake signal

The mP can emulate a DMA controller by asserting DACK

and EOP signals DRQ may be sampled by reading the

BSR In most cases the chip decode logic can be adapted

to this use for little or no cost See Section 70 for further

details

411 HALTING A DMA OPERATION

There are three ways to halt a DMA operation apart from a

chip or SCSI reset These methods are EOP phase mis-

match and resetting the DMA MODE bit in MR2

4111 End Of Process

EOP is asserted for a minimum period during the last DMA

cycle The EOP signal generates the End of DMA interrupt

EOP does not cause the MR2 DMA mode bit to be reset

4112 DMA Phase Mismatch

If a REQ goes active while there is a phase mismatch the

DMA will be halted and an interrupt generated The ASI will

stop driving the SCSI bus when the mismatch occurs A

phase mismatch is when the TCR phase bits do not match

the SCSI bus values

4113 DMA Mode Bit

If EOP is not used the best method is to reset the MR2 DMA

Mode bit This bit may be reset at any time and should be

reset after an End of DMA interrupt or a phase mismatch

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