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DP5380 数据表(PDF) 8 Page - National Semiconductor (TI) |
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DP5380 数据表(HTML) 8 Page - National Semiconductor (TI) |
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8 / 32 page  30 Register Description (Continued) DMA transfers the SCSI phase lines (CD MSG IO) must match the contents of the TCR for transfers to occur A phase mismatch halts DMA transfers and generates an in- terrupt Bit 7 Bit 0 xxxx REQ MSG CD IO Target Command Register This is a readwrite register and the value read reflects the state of each bit except bit 4 – 7 which always read 0 IO Assert IO Bit 0 0 Deassert IO 1 Assert SCSI IO signal The MR2 TARGET MODE bit must also be active CD Assert CD Bit 1 0 Deassert CD 1 Assert SCSI CD signal The MR2 TARGET MODE bit must also be active MSG Assert MSG Bit 2 0 Deassert MSG 1 Assert SCSI MSG signal The MR2 TARGET MODE bit must also be active REQ Assert REQ Bit 3 0 Deassert REQ 1 Assert SCSI REQ signal The MR2 TARGET MODE bit must also be active This bit is used to handshake SCSI data via programmed-IO SELECT ENABLE REGISTER (SER) 8 Bits HA 4 Write-Only This write-only register is used to program the SCSI device ID for the ASI to respond to during Selection or Reselection Phases Only one bit in the register should be set When SEL is true BSY false and the SER ID bit active an interrupt will occur This interrupt is reset or can be disabled by writing zero to this register Parity will also be checked during Selection or Reselection if the PCHK bit in MR2 is set Bit 7 Bit 0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Select Enable Register CURRENT SCSI BUS STATUS (CSB) 8 Bits HA 4 Read-Only This read-only register is used to monitor SCSI control sig- nals and the SCSI parity bit The SCSI lines are monitored during programmed-IO transfers and after an interrupt in order to determine the cause A bit is 1 if the corresponding SCSI signal is active Bit 7 Bit 0 RST BSY REQ MSG CD IO SEL DBP Current SCSI Bus Status BUS AND STATUS REGISTER (BSR) 8 Bits HA 5 Read-Only This read-only register is used to monitor SCSI signals not included in the CSB and internal status bits This register is read after an interrupt to determine the cause of an inter- rupt Bit 0 or 1 are set to 1 if the SCSI signal is active Bit 7 Bit 0 EDMA DRQ SPER INT PHSM BSY ATN ACK Bus Status Register ACK Acknowledge Bit 0 This bit reflects the state of the SCSI ACK Signal ATN Attention Bit 1 This bit reflects the state of the SCSI ATN Signal BSY Busy Error Bit 2 0 No Error 1 This SCSI BSY signal has become inactive while the MR2 BSY (Monitor BSY) bit is set This will cause an interrupt remove all ASI signals from the SCSI bus and reset the DMA MODE bit in MR2 PHSM Phase Match Bit 3 0 Phase Match The SCSI CD IO and MSG phase lines are continuously compared with the corresponding bits in the TCR The result of this comparison is reflected in this bit This bit must be 1 (phase matches) for DMA transfers A phase mismatch will stop DMA transfers and cause an interrupt INT Interrupt Request Bit 4 0 No Interrupt 1 Interrupt request active Set when an enabled interrupt condition occurs This bit reflects the state of the INT pin INT may be reset by performing a Reset ParityIn- terrupt (RPI) function SPER SCSI Parity Error Bit 5 0 No SCSI parity error 1 SCSI parity error occurred This bit remains set once an error occurs until the RPI function clears it The PCHK bit in MR2 must be set for a parity error to be checked and registered DRQ DMA Request Bit 6 0 No DMA request 1 DMA request active This bit reflects the state of the DRQ pin DRQ is reset by asserting DACK during a DMA cycle or by resetting the DMA bit in MR2 A Busy error will reset the MR2 DMA bit and thus will also clear DRQ A phase mismatch will not reset DRQ EDMA End of DMA Bit 7 0 Not end of DMA 1 Set when DACK EOP and either RD or WR are active simultaneously Normally occurs when the last byte is transferred by the DMA During DMA send operations the last byte transferred by the DMA may not have been transferred on SCSI so REQ and ACK should be monitored to verify when the last SCSI transfer is com- plete This bit is reset when the MR2 DMA bit is reset 8 |
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