DP5380 datasheet(13/32 Pages) NSC

13 / 32 page

40 Device Operation (Continued)

Resetting the bit disables all DMA logic and thus should

only be reset at the True End of DMA condition Additionally

all DMA logic is reset so this bit must be reset then set again

to carry out the next DMA phase

50 Interrupts

51 OVERVIEW

Before individually describing each interrupt an explanation

of the use of interrupts is required

52 USING INTERRUPTS

Interrupts are controlled by bits in MR2 if control is provided

Not all interrupts can be disabled under software control

When an interrupt occurs both the BSR and CSD register

must be read and analysed to determine the source of inter-

rupt Since status is NOT provided for each interrupt great

care should be exercised when determining the interrupt

source

53 SCSI PARITY ERROR

If SCSI parity checking is enabled via MR2 bit 5 an interrupt

can occur as a result of a read from CSD a selection

(re)selection or a DMA receive operation The parity error

bit (bit 5) in the BSR will be set if checking is enabled An

interrupt will occur if Enable Parity Interrupt (bit 4) of MR2 is

set The interrupt is reset by reading HA7 Following an in-

terrupt the BSR and CSD should contain the values shown

below

Bit 7

Bit 0

xxxx

EDMA DRQ SPER

INT

PHSM BSY

ATN

ACK

BSR

Bit 7

Bit 0

xxxx

RST

BSY

REQ

MSG

SEL

DBP

CSD

54 END OF DMA

If EOP is asserted during a DMA transfer bit 7 of the BSR

will be set and an interrupt generated if bit 3 of MR2 is 1

EOP is recognized when EOP DACK and either IOR or IOW

are all simultaneously active for a minimum period The in-

terrupt may be reset by reading HA 7 Following an interrupt

the BSR and CSD should contain the values shown below

Bit 7

Bit 0

x1x

EDMA DRQ SPER

INT

PHSM BSY

ATN

ACK

BSR

Bit 7

Bit 0

xxxx

RST

BSY

REQ

MSG

SEL

DBP

CSD

55 DMA PHASE MISMATCH

When the SCSI REQ goes active during a DMA operation

the contents of the TCR are compared with the SCSI phase

lines CD MSG and IO If the two do not match an inter-

rupt is generated This interrupt will occur as long as the

MR2 DMA bit is set (bit 1) ie it cannot be masked The

mismatch removes the ASI from driving the SCSI data bus

The interrupt may reset by reading HA 7 Following an inter-

rupt the BSR and CSD should contain the values shown

below

Bit 7

Bit 0

xxx

EDMA DRQ SPER

INT

PHSM BSY

ATN

ACK

BSR

Bit 7

Bit 0

xxxxx

RST

BSY

REQ

MSG

SEL

DBP

CSD

56 BUSY LOSS

If bit 2 MR2 is set the SCSI BSY signal is monitored and an

interrupt is generated if BSY is continuously inactive for at

least a BUS SETTLE DELAY (400 ns) This interrupt may be

reset by reading HA 7 Following an interrupt the BSR and

CSD should contain the values shown below where usually

CSD e 00

Bit 7

Bit 0

xxx

EDMA DRQ SPER

INT

PHSM BSY

ATN

ACK

BSR

Bit 7

Bit 0

xxxxxx

RST

BSY

REQ

MSG

SEL

DBP

CSD

57 (RE)SELECTION

An interrupt will be generated when SEL is active BSY is

inactive and the device ID is true The device ID is deter-

mined by the value in the SER If ANY non-zero bit in the

SER has its corresponding SCSI data bit active during se-

lection the device ID is true If IO is active this is a reselec-

tion The interrupt is disabled by writing all zeros to the SER

and reset by reading HA 7

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