DP5380 datasheet(11/32 Pages) NSC

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40 Device Operation (Continued)

The interface to the DMA controller uses the DRQ DACK

EOP lines in non-block mode Each byte is requested (DRQ)

and ack’d (DACK) Representative timing for a DMA read is

shown in

Figure 481

TLF9756 – 7

FIGURE 481 Non-Block DMA Timing

481 NON-BLOCK DMA

DMA operation involves programming the ASI with the set-

up parameters initiating the DMA cycles and checking for

correct operation when the completion interrupt is received

The DMA controller should be programmed with the data

byte count and the memory start address Methods of halt-

ing a DMA operation are covered in Section 411

Setting up the ASI requires enabling or disabling the follow-

ing Data bus driving DMA mode enable BSY monitoring

EOP interrupt parity checking parity interrupt TARGET

Mode bus phase

Once set up DMA should be initiated by writing to address 5

6 or 7 as appropriate The DMA controller should assert

EOP during the transfer of the last byte although this may

be done by the mP if the DMA transfers (n b 1) bytes and

the mP transfers the last byte See the application guide for

more details (Section 70)

Upon completion the mP should check the following as re-

quired End of DMA Parity Error Phase Match Busy Error

The end of DMA occurs as a response to EOP SCSI trans-

fers may still be underway so REQ and ACK must still be

checked to establish when the final byte is finished

The code below shows programming of the ASI in each of

the four DMA cases One of these cases is shown in a flow

diagram in Appendix A

Initiator Send

*DATA OUT PHASE*

Program DMA Controller

TCR

4 00h

*phase*

ICR

4 01h

*Assert DBUS*

MR2

4 0Eh

SDS

4 00

*Start DMA Send*

while (NOT interrupt)

idle

while (CSDREQ)

idle

*wait for last

SCSI byte

transfer so phase

is checked*

if(BSRBusy error OR NOT

(BSREnd of DMA))

error routine

else

*DMA End*

MR2

4 04h

*reset DMA bit*

ICR

4 0

Initiator Receive

*DATA IN PHASE*

Program DMA Controller

TCR

4 01h

*phase*

MR2

4 3Eh

SDI

4 0

*Start DMA Init

Rx*

while (NOT interrupt)

idle

*no need to wait for last SCSI handshake

done since DMA done implies it is

checked*

if(BSRparity error OR BSR

busy error

or NOT (BSR End of DMA)

do error routines

else

*End of DMA*

while (CSDREQ)

idle

*wait for REQ inactive

to deassert ACK*

MR2

4 04h

Target Receive

*DATA OUT PHASE*

Program DMA Controller

TCR

4 0

*phase*

ICR

4 08h

MR2

4 7Ah

*check parity*

SDT

4 0

*Start DMA Targ Rx*

while (not interrupt)

idle

*when End of DMA occurs the last byte

has been read and checked*

if(BSRparity error OR NOT(BSR

End of DMA)

error routine

else

*End of DMA*

while (BSRACK)

idle

*Not True End of DMA

so wait until SCSI

bus inactive before changing phase*

MR2

4 40h

change phase as required

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