DP5380 datasheet(4/32 Pages) NSC

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10 Functional Description (Continued)

The ASI arbitration logic controls arbitration for use of the

SCSI bus The mP programs the SCSI device ID into the

ASI then sets the ARBITRATE bit The INITIATOR COM-

MAND REGISTER (ICR) is read to determine when arbitra-

tion has started and whether it is won or lost

The BSY signal is continously monitored to detect bus dis-

connection and bus free phases The ASI incorporates an

on-board oscillator to determine Bus Settle Bus Free and

Arbitration Delays The oscillator tolerance guarantees all

timing to be within the SCSI specification

The ASI incorporates high-current drivers and SCHMITT

trigger receivers for interfacing directly to the SCSI bus This

feature reduces the chip count of any SCSI application

15 PARITY

The ASI provides for parity protection on the SCSI interface

The data bus has eight data bits and one parity bit The

parity may be enabled via a register bit A parity error can be

programmed to cause an interrupt

20 Pin Descriptions

Symbol

DIP

PCC

Type

Function

Chip Select

an active low enable for read or write operations accessing the register

selected by A02

A02

30 32 33

33 36 37

Address02

these three signals are used with CS RD and WR to address a

Read

an active low enable for reading an internal register selected by A02and

enabled by CS It also selects the Input Data Register when used with DACK

Write

an active low enable for writing an internal register selected by A02and

enabled by CS It also selects the Output Data Register when used with DACK

RESET

Reset

an active low input with a Schmitt trigger Clears all internal registers (SCSI

RST unaffected)

D07

1 40 – 34

2 44 – 38

I O

Data07

bidirectional TRI-STATE signals connecting the active high mP data

bus to the internal registers

INT

Interrupt

an active high output to the mP when an error has occurred an event

requires service or has completed

DRQ

DMA Request

an active high output asserted when the data register is ready to read

or written DRQ occurs only if DMA mode is enabled The signal is cleared by DACK

DACK

DMA Acknowledge

an active low input that resets DRQ and addresses the data

registers for input or output transfers DACK is used instead of CS by the DMA

controller

READY

Ready

an active high output used to control the speed of block mode DMA transfers

Ready goes active when the chip is ready to sendreceive data and remains inactive

after the transfer until the byte is sent or until the DMA mode bit is reset

EOP

End Of Process

an active low signal that terminates a block of DMA transfers It

should be asserted during the transfer of the last byte

DB07

92 10

103 11

I O

DB07 DBP

SCSI data bus with parity DB7 is the MSB and is the highest priority

during arbitration Parity is ODD Parity is always generated and can be optionally

DBP

checked Parity is not valid during arbitration

RST

Reset

SCSI reset monitored and can be set by ASI

BSY

Busy

indicates the SCSI bus is being used Can be driven by TARGET or

INITIATOR

SEL

Select

used by the INITIATOR to select a TARGET or by the TARGET to reselect an

INITIATOR

ACK

Acknowledge

driven by the INITIATOR and received by the TARGET as part of the

REQACK handshake

ATN

Attention

driven by the INITIATOR to indicate an attention condition to the

TARGET

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