DP5380 datasheet(7/32 Pages) NSC

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30 Register Description (Continued)

ACK Assert Acknowledge

Bit 4

Deassert ACK

Assert SCSI ACK signal The MR2 TARGET MODE bit

must also be false to assert the signal

Reading the ICR reflects the state of this bit

DIFF Differential Enable

Bit 5

Write

This bit must be reset to 0

Do not use Reserved for future use on a differential

pair device

LA Lost Arbitration

Bit 5

Read

Normally reset to 0 to show arbitration not lost or not

enabled

Will be set when the ASI loses arbitation ie when SEL

is true during arbitration AND the Assert SEL bit of this

A 1 in this bit means the ASI has arbitrated for the bus

asserted BSY and its ID on the data bus and another device

has asserted SEL The ARBITRATE bit in MR2 must be set

to enable arbitration

TEST Test Mode Enable

Bit 6

Write

Output drivers are enabled

Output drivers disabled

AIP Arbitration In Progress

Bit 6

Read

Normally 0 to show no arbitration in progress

Set when the ASI has detected BUS FREE phase and

asserted BSY and the Output Data Register contents

onto the SCSI data bus This bit remains set until arbi-

tration is disabled

RST Assert RST

Bit 7

Deassert RST

Assert SCSI RST signal RST is asserted as long as this

bit is 1 or until a mP Reset (RESET)

After this bit is set the INT pin goes active and internal regis-

ters reset (except for the interrupt latch MR2 TARGET

MODE bit and this bit Reading the ICR reflects the state of

this bit

MODE REGISTER 2 (MR2)

8 Bits

HA2

Read-Write

This register is used to program basic operating conditions

in the ASI Operation as TARGET or INITIATOR DMA

mode and type as well as some interrupt controls are set via

this register This is a ReadWrite register and when read

the value reflects the state of each bit

Bit 7

Bit 0

BLK

TARG PCHK PINT

EOP

BSY

DMA

ARB

Mode Register 2

ARB Arbitrate

Bit 0

Disable arbitration

Enable arbitration The ASI will wait for a BUS FREE

phase then arbitrate for the bus Before setting this bit

the Output Data Register should contain the SCSI de-

vice IDa single bit set only The status of the arbitra-

tion process is given in the AIP and LA bits (6 5) in the

Initiator Command Register

DMA DMA Mode

Bit 1

Disable DMA mode

Enable DMA operation This bit should be set then one

of address 5 to 7 written to start DMA The TARGET

MODE bit in the ICR and the phase lines in the TCR

should have been set appropriately The DBUS bit in

the ICR must be set for DMA operations BSY must be

active in order to set this bit The phase lines must

match the contents of the TCR during the actual trans-

fers In DMA mode ASI logic automatically controls the

REQ ACK handshakes

This bit should be reset by a mP write to stop any DMA

transfer An EOP signal will not reset this bit During

DMA CS and DACK should not be active simultaneous-

This bit will be reset if BSY is lost during DMA mode

BSY Monitor Busy

Bit 2

Disable BSY monitor

Monitor SCSI BSY signal and interrupt when BSY goes

inactive When this bit goes active the lower 6 bits of

the ICR are reset and all signals removed from the

SCSI bus This is used to check for valid TARGET con-

nection

EOP Enable EOP Interrupt

Bit 3

No interrupt for EOP

Interrupt after valid EOP condition

PINT Enable SCSI Parity Interrupt

Bit 4

No interrupt on SCSI parity error

When SCSI parity is enabled via the PCHK bit setting

this bit enables an interrupt upon a SCSI parity error

PCHK Enable SCSI Parity Checking

Bit 5

No SCSI parity checking

Enable checking of SCSI parity during read operations

This applies to either programmed IO or DMA mode

TARG Target Mode

Bit 6

Initiator Mode

Target Mode

BLK Block Mode DMA

Bit 7

Non-block DMA

When set along with DMA bit (1) enable block mode

DMA transfers In block mode the READY line is used

to handshake each byte with the DMA controller in-

stead of the DRQDACK handshake used in non-block

mode

TARGET COMMAND REGISTER (TCR)

4 Bits

HA 3

Read-Write

This register is used to control TARGET SCSI signals and to

program the desired phase during INITIATOR mode During

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