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DP5380 数据表(PDF) 1 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
部件名 DP5380
功能描述  Asynchronous SCSI Interface (ASI)
PDF  32 Pages
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制造商  NSC [National Semiconductor (TI)]
网页  http://www.national.com
标志 NSC - National Semiconductor (TI)

DP5380 数据表(HTML) 1 Page - National Semiconductor (TI)

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TLF9756
May 1989
DP5380 Asynchronous SCSI Interface (ASI)
General Description
The DP5380 ASI is a CMOS device designed to provide a
low cost high performance Small Computer Systems Inter-
face It complies with the ANS X3131-1986 SCSI standard
as defined by the ANSI X3T92 committee It can act as
both INITIATOR and TARGET making it suitable for any
application The ASI supports selection reselection arbitra-
tion and all other bus phases High-current open-drain driv-
ers on chip reduce application chip count by interfacing di-
rect to the SCSI bus An on-chip oscillator provides all tim-
ing delays
The DP5380 is pin and program compatible with the NMOS
NCR5380 device NCR5380 or AM5380 applications can
use it with no changes to hardware or software The
DP5380 is available in a 40-pin DIP or a 44-pin PCC
The ASI is intended to be used in a microprocessor based
application and achieves maximum performance with a
DMA controller The device is controlled by reading and
writing several internal registers A standard non-multi-
plexed address and data bus easily fits any mP environment
Data transfers can be performed by programmed-IO pseu-
do-DMA or via a DMA controller The ASI easily interfaces
to a DMA controller using normal or Block Mode The ASI
can be used in either a polled or interrupt-driven environ-
ment
Features
SCSI Interface
Y
Supports TARGET and INITIATOR roles
Y
Parity generation with optional checking
Y
Arbitration support
Y
Direct controlmonitoring of all SCSI signals
Y
High current outputs drive SCSI bus directly
Y
Faster and improved timing
Y
Very low SCSI bus loading
mP Interface
Y
Memory or IO-mapped control transfers
Y
Programmed-IO or DMA data transfers
Y
Normal or Block-mode DMA
Y
Fast DMA handshake timing
Connection Diagram
TLF9756 – 1
Table of Contents
10 FUNCTIONAL DESCRIPTION
20 PIN DESCRIPTION
30 REGISTER DESCRIPTION
40 DEVICE OPERATION
50 INTERRUPTS
60 RESET CONDITIONS
70 APPLICATION GUIDE
80 ABSOLUTE MAXIMUM RATINGS
90 DC ELECTRICAL CHARACTERISTICS
100 AC ELECTRICAL CHARACTERISTICS
A1 FLOWCHARTS
A2 REGISTER CHART
TRI-STATE
is a registered trademark of National Semiconductor Corporation
PAL
is a registered trademark of and used under license from Monolithic Memories Inc
C1995 National Semiconductor Corporation
RRD-B30M115Printed in U S A


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