DP5380 datasheet(9/32 Pages) NSC

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30 Register Description (Continued)

START DMA SEND (SDS)

0 Bits

HA 5

Write-Only

This write-only register is used to start a DMA send opera-

tion A write of don’t-care data should be the last thing done

by the mP The MR2 DMA BLK and TARG bits must have

been programmed previously

Bit 7

Bit 0

xxxxxxxx

Start DMA Send

START DMA TARGET RECEIVE (SDT)

0 Bits

HA 6

Write-Only

This write-only register is used to start a DMA Target Re-

ceive operation Same comments as SDS apply

INPUT DATA REGISTER (IDR)

8 Bits

HA 6

Read-Only

This read-only register contains the SCSI data last latched

during a DMA receive Each byte from SCSI is latched into

this register automatically by the ASI DMA logic A DMA

read (DACK and RD) automatically selects this register Pro-

grammed-IO SCSI data reads should use the CSD (HA8)

START DMA INITIATOR RECEIVE (SDI)

0 Bits

HA 7

Write-Only

This write-only register is used to start a DMA INITIATOR

Receive Operation Same comments as SDS apply

RESET PARITYINTERRUPT (RPI)

0 Bits

HA 7

Read-Only

This read-only register is used to reset the parity and inter-

rupt latches Reading this register resets the SCSI parity

Busy Loss and Interrupt Request latches

40 Device Operation

41 GENERAL

This section describes overall operation of the ASI More

detailed information of data transfers interrupts and reset

conditions are covered in later sections The operation de-

scription covers mP accesses SCSI bus monitoring arbitra-

tion selection reselection programmed-IO DMA inter-

rupts Programming and timing details are covered

For information regarding interfacing to mP’s and DMA con-

trollers refer to Section 70

In the descriptions following program examples are given in

pseudo-C This processor-independent approach should be

clearest These are backed up by flow charts in Appendix

42 mP ACCESSES

The mP accesses the EASI via the CS RD WR and address

and data lines in order to readwrite the registers

Figure 42

shows typical timing Note the use of non-multiplexed ad-

dress and data lines

43 SCSI BUS MONITORINGDRIVING

The SCSI bus may be monitored or driven at any time Each

bus signal is buffered and inverted by the ASI and can be

read via the CSB BSR and CSD registers An active SCSI

readsa1inthe status registers

TLF9756 – 6

FIGURE 42 mP Cycles

Each SCSI signal may be asserted by setting a bit in the

TCR or ICR Setting the bit to 1 asserts the SCSI signal

The following code demonstrates a byte transferred via pro-

grammed-IO in INITIATOR mode

*Transfer one byte as Initiator*

while (NOT (TCRREQ))

* wait till TARGET asserts REQ *

data

4 input (CSD)

* parity is checked if enabled*

output (ICR

Assert ACK)

while (TCRREQ)

* wait till TARGET deasserts REQ *

output (ICR

* deassert ACK

ready for next byte *

44 ARBITRATION

This sub-section describes the arbitration support provided

by the ASI and how to program it

Since the SCSI arbitration process requires signal sequenc-

ing too fast for mP’s hardware support is provided by the

ASI The arbitration process is enabled by bit 0 MR2 (ARB)

Prior to setting this bit the ODR should be programmed with

the device’s SCSI IDa single bit

The ASI will monitor the bus for a BUS FREE phase The

BSY signal is continuously monitored If continuously inac-

tive for at least a SCSI Bus Settle Delay (400 ns) and SEL is

inactive a valid Bus Free Phase exists After a period of

SCSI Bus Free Delay (800 ns) the ASI asserts BSY and the

ODR onto the SCSI data bus The mP should poll the ICR to

determine when arbitration has started The AIP bit in the

ICR is set when the Bus Free Phase is detected and the

EASI is beginning the Bus Free Delay Following the Bus

Free Delay a 22 ms SCSI Arbitration Delay is required be-

fore examining the data bus to resolve the priorities of the

ID bits This delay must be implemented in firmware The

ICR Lost Arbitration (LA) bit must be examined to determine

whether arbitration is lost The LA bit is set if another

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