Not Recommended for New Designs

bq28550-R1

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SLUSAS4A – OCTOBER 2012 – REVISED SEPTEMBER 2014

NOTE

When the CHG FET or DSG FET is turned OFF due to fault conditions, bus

communication is not valid. The bus communication will only be activated by removal of

the fault condition (see Table 1).

7.5.8 Regulator

Regulator out voltage is fixed at typically 2.5 V with a minimum output capacitance of 0.1 µF (0.47 µF typ). There

is an internal current limit designed for 60 mA (typ) when output is shorted to GND. When VDD is over 8.0 V

(typ), the regulator is turned off for the safety of the package dissipation.

7.6 Feature Description

7.6.1 Auto-Calibration

The bq28550-R1 device provides an auto-calibration feature that measures the voltage offset error across SRP

and SRN from time-to-time as operating conditions change. It subtracts the resulting offset error from the normal

sense resistor voltage, VSR, for maximum measurement accuracy.

Auto-calibration of the ADC begins on entry to SLEEP mode, except if Temperature() is

≤ 5°C or Temperature()

≥ 45°C.

The gas gauge also performs a single offset when (1) the condition of AverageCurrent()

≤ 100 mA and (2) {cell

voltage change since the last offset calibration

≥ 256 mV} or {temperature change since last offset calibration is

greater than 80°C for

≥ 60 s}.

Capacity and current measurements continue at the last measured rate during the offset calibration when these

measurements cannot be performed. If the battery voltage drops more than 32 mV during the offset calibration,

the load current has likely increased considerably and the offset calibration will be stopped.

7.6.2 Serial 2-Wire Communication System

The 2-wire communication bus supports a slave-only device in a single- or multi-slave configuration with a single-

or multi-master configuration. The device can be part of a shared bus by the unique setting of the 7-bit slave

address. The 2-wire communication is bi-directional, consisting of a serial data line (SDA) and a clock line (SCL).

In receive mode, the SDA terminal operates as an input; whereas, when the device is returning data to the

master, the SDA operates as an open-drain output with an external resistive pull-up. The master device controls

the initiation of the transaction on the bus line.

Data Transfer: Each data bit is transferred during an SCL clock cycle (transition from low-to-high and then high-

to-low). The data signal on the SDA (logic level) must be stable during the high period of the SCL clock pulse. A

change in the SDA logic when SCL is high is interpreted as a START or STOP control signal. If a transfer is

interrupted by a STOP condition, the partial byte transmission shall not be latched. Only the prior messages

transmitted and acknowledged are latched.

Data Format: The data is an 8-bit format with the most significant bit (MSB) first and the least significant bit

(LSB) followed by an Acknowledge bit. If the slave cannot receive or transmit any byte of data until it services a

priority interrupt, it can pull the SCL line low to force the master device into wait state. The slave, once ready to

resume data transfer, can release the SCL line (get out of wait state).

Bus Idle: The bus is considered idle or busy when no master device has control of this device. The SDA and

SCL lines are high when the bus is idle. The appropriate method to go into the STOP condition is to ensure the

bus returns to idle state.

START (S) and STOP (P) Conditions: To initiate communications, the master device transitions the SDA line

from high-to-low when the SCL is high. Conversely, to STOP the communication, the SDA goes low-to-high

when the SCL is high. To continue communication without terminating one transaction and beginning another, a

repeated START (Sr) method can be used without a STOP condition being initiated. These are the only

conditions (START or STOP) when SDA transitions when SCL is high.

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