BQ28550-R1 datasheet(3/42 Pages) TI1

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DOUT

COUT

BAT

VREG

VSS

SRP

SRN

SDA

SCL

GPIO

Not Recommended for New Designs

bq28550-R1

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SLUSAS4A – OCTOBER 2012 – REVISED SEPTEMBER 2014

5 Pin Configuration and Functions

Pin Functions

PIN NUMBER

PIN NAME

I/O (1)

DESCRIPTION

DOUT

The output of gate drive for discharge FET

COUT

The output of gate drive for charge FET

Analog input pin connected to the PACKN through a 510-

Ω resistor. Overcurrent and short-

circuit protection circuits use the voltage across VM and VSS to detect if excessive charge or

discharge current is flowing through the protection FETs.

BAT

Cell voltage measurement input. ADC input. Connect a 0.1-µF ceramic capacitor to VSS.

2.5-V output voltage of the internal integrated LDO. Connect a 0.1-µF ceramic capacitor to

VREG

VSS.

VSS

Device ground

Analog input pin connected to the internal Coulomb counter where SRP is nearest the

SRP

CELL– connection. Connect to a 5-m

Ω to 20-mΩ sense resistor.

Analog input pin connected to the internal Coulomb counter where SRN is nearest the

SRN

PACKN connection. Connect to a 5-m

Ω to 20-mΩ sense resistor.

Pack thermistor voltage sense (use 103AT-type thermistor), ADC input

SDA

I/O

Serial Data interface for SMBus

SCL

Serial Clock interface for SMBus

GPIO

I/O

General Purpose I/O for configurable function (CFET Control or ALERT output)

PWPD

I/O

Texas Instruments recommends connecting the power pad to VSS on the PCB.

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