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VT82C596 数据表(PDF) 65 Page - List of Unclassifed Manufacturers

部件名 VT82C596
功能描述  PCI INTEGRATED PERIPHERAL CONTROLLER
PDF  96 Pages
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制造商  ETC [List of Unclassifed Manufacturers]
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标志 ETC - List of Unclassifed Manufacturers

VT82C596 数据表(HTML) 65 Page - List of Unclassifed Manufacturers

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VT82C596B
Revision 0.3 June 17, 1999
-59-
Function 3 Registers - Power Management and SMBus
7HFKQRORJLHV ,QF
:H &RQQHFW
:H &RQQHFW
Power Management-Specific PCI Configuration Registers
Offset 40 - Debounce Control...........................................RW
7-6
Reserved
........................................ always reads 0
5
Debounce LID and PWRBTN# Inputs for 200us
0
Disable ...................................................default
1Enable
4-0
Reserved
........................................ always reads 0
Offset 41 - General Configuration (00h)......................... RW
7
I/O Enable for ACPI I/O Base
0
Disable access to ACPI I/O block.......... default
1
Allow access to Power Management I/O
Register Block (see offset 4B-48 to set the
base address for this register block).
The
definitions of the registers in the Power
Management I/O Register Block are included
later in this document, following the Power
Management Subsystem overview.
6
ACPI Timer Reset
0
Disable................................................... default
1Enable
5-4
Reserved (Do Not Program) ...................... default = 0
3
ACPI Timer Count Select
0
24-bit Timer........................................... default
1
32-bit Timer
2
RTC Enable Signal Gated with PSON (SUSC#) in
Soft-Off Mode
0
Disable................................................... default
1Enable
1
Clock Throttling Clock Selection
0
32 usec (512 usec cycle time) ................ default
1
1 msec (16 msec cycle time)
0
Reserved (Do Not Program) ...................... default = 0



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