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VT82C596 数据表(PDF) 79 Page - List of Unclassifed Manufacturers |
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VT82C596 数据表(HTML) 79 Page - List of Unclassifed Manufacturers |
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79 / 96 page ![]() VT82C596B Revision 0.3 June 17, 1999 -73- Function 3 Registers - Power Management and SMBus 7HFKQRORJLHV ,QF :H &RQQHFW :H &RQQHFW General Purpose Power Management Registers I/O Offset 21-20 - General Purpose Status (GP_STS).RWC 15 Reserved ........................................ always reads 0 14 USB Wakeup Status for STR/STD/Soff (UW_STS) 13 Reserved ........................................ always reads 0 12 Battery Low Status (BL_STS) This bit is set when the BATLOW# input is asserted low. 11 Notebook Lid Status (LID_STS) This bit is set when the LID input detects the edge selected by Rx2C bit-7 (0=rising, 1=falling). 10 Thermal Detect Status (THRM_STS) This bit is set when the THRM# input detects the edge selected by Rx2C bit-6 (0=rising, 1=falling). 9 USB Resume Status (USB_STS) This bit is set when a USB peripheral generates a resume event. 8 Ring Status (RI_STS) This bit is set when the RI# input is asserted low. 7 EXTSMI7 Toggle Status (XSMI7_STS) This bit is set when the GPI17 pin is toggled. 6 EXTSMI6 Toggle Status (XSMI6_STS) This bit is set when the GPI16 pin is toggled. 5 EXTSMI5 Toggle Status (XSMI5_STS) This bit is set when the GPI15 pin is toggled. 4 EXTSMI4 Toggle Status (XSMI4_STS) This bit is set when the GPI4 pin is toggled. 3 EXTSMI3 Toggle Status (XSMI3_STS) This bit is set when the GPI3 pin is toggled. 2 EXTSMI2 Toggle Status (XSMI2_STS) This bit is set when the GPI2 pin is toggled. 1 PME# Status (PME_STS) This bit is set when the GPI1 pin is asserted high. 0 EXTSMI# Status (EXT_STS) This bit is set when the EXTSMI# pin is asserted low. Note that the above bits correspond one for one with the bits of the General Purpose SCI Enable and General Purpose SMI Enable registers at offsets 22 and 24: an SCI or SMI is generated if the corresponding bit of the General Purpose SCI or SMI Enable registers, respectively, is set to one. The above bits are set by hardware only and can only be cleared by writing a one to the desired bit. I/O Offset 23-22 - General Purpose SCI Enable ............ RW 15 Reserved ........................................ always reads 0 14 Enable SCI on setting of the UW_STS bit .....def=0 13 Reserved ........................................ always reads 0 12 Enable SCI on setting of the BL_STS bit ......def=0 11 Enable SCI on setting of the LID_STS bit .....def=0 10 Enable SCI on setting of the THRM_STS bit def=0 9 Enable SCI on setting of the USB_STS bit ....def=0 8 Enable SCI on setting of the RI_STS bit .......def=0 7 Enable SCI on setting of the XSMI7_STS bit def=0 6 Enable SCI on setting of the XSMI6_STS bit def=0 5 Enable SCI on setting of the XSMI5_STS bit def=0 4 Enable SCI on setting of the XSMI4_STS bit def=0 3 Enable SCI on setting of the XSMI3_STS bit def=0 2 Enable SCI on setting of the XSMI2_STS bit def=0 1 Enable SCI on setting of the PME_STS bit....def=0 0 Enable SCI on setting of the EXT_STS bit ....def=0 These bits allow generation of an SCI using a separate set of conditions from those used for generating an SMI. I/O Offset 25-24 - General Purpose SMI Enable ........... RW 15 Reserved ........................................ always reads 0 14 Enable SMI on setting of the UW_STS bit ....def=0 13 Reserved ........................................ always reads 0 12 Enable SMI on setting of the BL_STS bit .....def=0 11 Enable SMI on setting of the LID_STS bit ....def=0 10 Enable SMI on setting of the THRM_STS bit def=0 9 Enable SMI on setting of the USB_STS bit ...def=0 8 Enable SMI on setting of the RI_STS bit ......def=0 7 Enable SMI on setting of the XSMI7_STS bitdef=0 6 Enable SMI on setting of the XSMI6_STS bitdef=0 5 Enable SMI on setting of the XSMI5_STS bitdef=0 4 Enable SMI on setting of the XSMI4_STS bitdef=0 3 Enable SMI on setting of the XSMI3_STS bitdef=0 2 Enable SMI on setting of the XSMI2_STS bitdef=0 1 Enable SMI on setting of the PME_STS bit...def=0 0 Enable SMI on setting of the EXT_STS bit....def=0 These bits allow generation of an SMI using a separate set of conditions from those used for generating an SCI. |
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