VT82C596 datasheet(80/96 Pages) ETC

80 / 96 page

VT82C596B

Revision 0.3 June 17, 1999

-74-

Function 3 Registers - Power Management and SMBus

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Generic Power Management Registers

I/O Offset 29-28 - Global Status....................................RWC

GPIO Range 1 Access Status (GP_R1_STS).. def=0

GPIO Range 0 Access Status (GP_R0_STS).. def=0

GP3 Timer Timeout Status (GP3_TO_STS).. def=0

GP2 Timer Timeout Status (GP3_TO_STS).. def=0

SerIRQ SMI Status (SIRQ_SM_STS)............ def=0

10-9 Reserved

........................................ always reads 0

PCKRUN# Resume Status (PR_RSM_STS).. def=0

This bit is set when PCI bus peripherals wake up the

system by asserting PCKRUN#

Primary IRQ Resume Status (PI_RSM_STS) def=0

This bit is set at the occurrence of primary IRQs as

defined in Rx45-44 of PCI configuration space

Software SMI Status (SW_SMI_STS)............ def=0

This bit is set when the SMI_CMD port (offset 2F) is

written.

BIOS Status (BIOS_STS) ................................ def=0

This bit is set when the GBL_RLS bit is set to one

(typically by the ACPI software to release control of

the SCI/SMI lock). When this bit is reset (by writing

a one to this bit position) the GBL_RLS bit is reset at

the same time by hardware.

Legacy USB Status (LEG_USB_STS) ............ def=0

This bit is set when a legacy USB event occurs.

GP1 Timer Time Out Status (GP1_TO_STS) def=0

This bit is set when the GP1 timer times out.

GP0 Timer Time Out Status (GP0_TO_STS) def=0

This bit is set when the GP0 timer times out.

Secondary

Event

Timer

Time

Out

Status

(ST_TO_STS) ................................................... def=0

This bit is set when the secondary event timer times

out.

Primary Activity Status (PACT_STS)............ def=0

This bit is set at the occurrence of any enabled

primary system activity (see the Primary Activity

Detect Status register at offset 30h and the Primary

Activity Detect Enable register at offset 34h). After

checking this bit, software can check the status bits in

the Primary Activity Detect Status register at offset

30h to identify the specific source of the primary

event. Note that setting this bit can be enabled to

reload the GP0 timer (see bit-0 of the GP Timer

Reload Enable register at offset 38).

Note that SMI can be generated based on the setting of any of

the above bits (see the offset 2Ah Global Enable register bit

descriptions in the right hand column of this page).

The bits in this register are set by hardware only and can only

be cleared by writing a one to the desired bit position.

I/O Offset 2B-2A - Global Enable ................................... RW

GPIO Range 1 Access Enable (GP_R1_EN) ..def=0

GPIO Range 0 Access Enable (GP_R0_EN) ..def=0

GP3 Timer Timeout Enable (GP3_TO_EN) ..def=0

GP2 Timer Timeout Enable (GP3_TO_EN) ..def=0

SerIRQ SMI Enable (SIRQ_SM_EN) ............def=0

10-9 Reserved

........................................ always reads 0

PCKRUN# Resume Enable (PR_RSM_EN) ..def=0

This bit may be set to trigger an SMI to be generated

when the PR_RSM_STS bit is set.

Primary IRQ Resume Enable (PI_RSM_EN) def=0

This bit may be set to trigger an SMI to be generated

when the PI_RSM_STS bit is set.

Software SMI Enable (SW_SMI_EN) ............def=0

This bit may be set to trigger an SMI to be generated

when the SW_SMI_STS bit is set.

BIOS Enable (BIOS_EN).................................def=0

This bit may be set to trigger an SMI to be generated

when the BIOS_STS bit is set.

Legacy USB Enable (LEG_USB_EN).............def=0

This bit may be set to trigger an SMI to be generated

when the LEG_USB_STS bit is set.

GP1 Timer Time Out Enable (GP1_TO_EN) def=0

This bit may be set to trigger an SMI to be generated

when the GP1_TO_STS bit is set.

GP0 Timer Time Out Enable (GP0_TO_EN) def=0

This bit may be set to trigger an SMI to be generated

when the GP0_TO_STS bit is set.

Secondary

Event

Timer

Time

Out

Enable

(ST_TO_EN) .....................................................def=0

This bit may be set to trigger an SMI to be generated

when the ST_TO_STS bit is set.

Primary Activity Enable (PACT_EN) ............def=0

This bit may be set to trigger an SMI to be generated

when the PACT_STS bit is set.

VT82C596 数据表(PDF) 80 Page - List of Unclassifed Manufacturers

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VT82C596 数据表(PDF) 80 Page - List of Unclassifed Manufacturers

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