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VT82C596 数据表(PDF) 68 Page - List of Unclassifed Manufacturers |
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VT82C596 数据表(HTML) 68 Page - List of Unclassifed Manufacturers |
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68 / 96 page ![]() VT82C596B Revision 0.3 June 17, 1999 -62- Function 3 Registers - Power Management and SMBus 7HFKQRORJLHV ,QF :H &RQQHFW :H &RQQHFW Offset 53-50 – GP0/1 Timer Control (0000 0000h).........RW 31-30 Conserve Mode Timer Count Value 00 1/16 second ............................................default 01 1/8 second 10 1 second 11 1 minute 29 Conserve Mode Status This bit reads 1 when in Conserve Mode 28 Conserve Mode Enable 0 Disable ...................................................default 1Enable 27-26 Secondary Event Timer Count Value 00 2 milliseconds.........................................default 01 64 milliseconds 10 ½ second 11 by EOI + 0.25 milliseconds 25 Secondary Event Occurred Status This bit reads 1 to indicate that a secondary event has occurred (to resume the system from suspend) and the secondary event timer is counting down. 24 Secondary Event Timer Enable 0 Disable ...................................................default 1Enable 23-16 GP1 Timer Count Value (base defined by bits 5-4) Write to load count value; Read to get current count 15-8 GP0 Timer Count Value (base defined by bits 1-0) Write to load count value; Read to get current count 7 GP1 Timer Start On setting this bit to 1, the GP1 timer loads the value defined by bits 23-16 of this register and starts counting down. The GP1 timer is reloaded at the occurrence of certain peripheral events enabled in the GP Timer Reload Enable Register (Power Management I/O Space Offset 38h). If no such event occurs and the GP1 timer counts down to zero, then the GP1 Timer Timeout Status bit is set to one (bit-3 of the Global Status register at Power Management Register I/O Space Offset 28h). Additionally, if the GP1 Timer Timeout Enable bit is set (bit-3 of the Global Enable register at Power Management Register I/O Space Offset 2Ah), then an SMI is generated. 6 GP1 Timer Automatic Reload This bit is set to one to enable the GP1 timer to reload automatically after counting down to 0. 5-4 GP1 Timer Base 00 Disable ...................................................default 01 1/4 msec 10 1 second 11 1 minute 3 GP0 Timer Start On setting this bit to 1, the GP0 timer loads the value defined by bits 15-8 of this register and starts counting down. The GP0 timer is reloaded at the occurrence of certain peripheral events enabled in the GP Timer Reload Enable Register (Power Management I/O Space Offset 38h). If no such event occurs and the GP0 timer counts down to zero, then the GP0 Timer Timeout Status bit is set to one (bit-2 of the Global Status register at Power Management Register I/O Space Offset 28h). Additionally, if the GP0 Timer Timeout Enable bit is set (bit-2 of the Global Enable register at Power Management Register I/O Space Offset 2Ah), then an SMI is generated. 2 GP0 Timer Automatic Reload This bit is set to one to enable the GP0 timer to reload automatically after counting down to 0. 1-0 GP0 Timer Base 00 Disable................................................... default 01 1/16 second 10 1 second 11 1 minute |
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