VT82C596 datasheet(76/96 Pages) ETC

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VT82C596B

Revision 0.3 June 17, 1999

-70-

Function 3 Registers - Power Management and SMBus

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Power Management I/O-Space Registers

Basic Power Management Control and Status

I/O Offset 1-0 - Power Management Status .................RWC

The bits in this register are set only by hardware and can be

reset by software by writing a one to the desired bit position.

Wakeup Status (WAK_STS) ................... default = 0

This bit is set when the system is in the suspend state

and an enabled resume event occurs. Upon setting

this bit, the system automatically transitions from the

suspend state to the normal working state (from C3 to

C0 for the processor).

14-12 Reserved

........................................ always reads 0

Power Status (PWR_STS)........................ default = 0

This bit is set by abnormal power off.

RTC Status (RTC_STS) ........................... default = 0

This bit is set when the RTC generates an alarm (on

assertion of the RTC IRQ signal).

Sleep Button Status (SB_STS)................. default = 0

This bit is set when the sleep button (SLPBTN# /

GPI13) is pressed.

Power Button Status (PB_STS)............... default = 0

This bit is set when the PWRBTN# signal is asserted

LOW.

If the PWRBTN# signal is held LOW for

more than four seconds, this bit is cleared and the

system will transition into the soft off state.

7-6

Reserved

........................................ always reads 0

Global Status (GBL_STS)........................ default = 0

This bit is set by hardware when BIOS_RLS is set

(typically by an SMI routine to release control of the

SCI/SMI lock). When this bit is cleared by software

(by writing a one to this bit position) the BIOS_RLS

bit is also cleared at the same time by hardware.

Bus Master Status (BM_STS) ................. default = 0

This bit is set when a system bus master requests the

system bus.

All PCI master, ISA master and ISA

DMA devices are included.

3-1

Reserved

........................................ always reads 0

Timer Carry Status (TMR_STS)............. default = 0

The bit is set when the 23

rd (31st) bit of the 24 (32)

bit ACPI power management timer changes.

I/O Offset 3-2 - Power Management Enable .................. RW

The bits in this register correspond to the bits in the Power

Management Status Register at offset 1-0.

Reserved

........................................ always reads 0

14-11 Reserved

........................................ always reads 0

RTC Enable (RTC_EN)............................ default = 0

This bit may be set to trigger either an SCI or an SMI

(depending on the setting of the SCI_EN bit) to be

generated when the RTC_STS bit is set.

Sleep Button Enable (SB_EN) ................. default = 0

This bit may be set to trigger either an SCI or SMI

when the SB_STS bit is set.

Power Button Enable (PB_EN) .............. default = 1

This bit may be set to trigger either an SCI or an SMI

(depending on the setting of the SCI_EN bit) to be

generated when the PB_STS bit is set.

7-6

Reserved

........................................ always reads 0

Global Enable (GBL_EN)......................... default = 0

This bit may be set to trigger either an SCI or an SMI

(depending on the setting of the SCI_EN bit) to be

generated when the GBL_STS bit is set.

Reserved

........................................ always reads 0

3-1

Reserved

........................................ always reads 0

ACPI Timer Enable (TMR_EN) .............. default = 0

This bit may be set to trigger either an SCI or an SMI

(depending on the setting of the SCI_EN bit) to be

generated when the TMR_STS bit is set.

VT82C596 数据表(PDF) 76 Page - List of Unclassifed Manufacturers

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VT82C596 数据表(PDF) 76 Page - List of Unclassifed Manufacturers

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