DP8430V datasheet(32/56 Pages) NSC

32 / 56 page

70 RAS and CAS Configuration Modes (Continued)

75 PAGEBURST MODE

In a static column page or burst mode system the least

significant bits must be tied to the column address in order

to ensure that the pageburst accesses are to sequential

memory addresses as shown in

Figure 28

In a nibble

mode system the least significant bits must be tied to the

highest column and row address bits in order to ensure that

sequential address bits are the ‘‘nibble’’ bits for nibble mode

accesses

(Figure 28) The ECAS inputs may then be tog-

gled with the DP8430V31V32V’s address latches in fall-

through mode while AREQ is asserted The ECAS inputs

can also be used to select individual bytes When using nib-

ble mode DRAMS the third and fourth address bits can be

tied to the bank select inputs to perform memory interleav-

ing In page or static column modes the two address bits

after the page size can be tied to the bank select inputs to

select a new bank if the page size is exceeded

TLF11118 – 43

See table below for row column

bank address bit map A0 A1 are used for byte addressing in this example

Addresses

Nibble Mode

Page ModeStatic Column Mode Page Size

256 BitsPage

512 BitsPage

1024 BitsPage

2048 BitsPage

Column

C9R9 e A2A3

C0 – 7 e A2–9

C0–8 e A2–10

C0–9 e A2–11

C0–10 e A2–12

Address

C0 – 8 e X

C8–10 e X

C910 e X

C10 e X

Row

Address

A10

A11

A12

A13

A11

A12

A13

A14

Assume that the least significant address bits are used for byte addressing Given a 32-bit system A0A1 would be

used for byte addressing

X e DON’T CARE the user can do as he pleases

Nibble mode values for R and C assume a system using 1 Mbit DRAMs

FIGURE 28 Page Static Column Nibble Mode System

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