DP8430V datasheet(11/56 Pages) NSC

11 / 56 page

30 Programming and Resetting (Continued)

33 PROGRAMMING BIT DEFINITIONS

(Continued)

Symbol

Description

R5 R4

WAIT DTACK during Burst (See Section 512 or 522)

0 0

NO WAIT STATES If R7 e 0 during programming WAIT will remain negated during burst portion of access

If R7 e 1 programming DTACK will remain asserted during burst portion of access

0 1

1T If R7 e 0 during programming WAIT will assert when the ECAS inputs are negated with AREQ asserted

WAIT will negate from the positive edge of CLK after the ECASs have been asserted

If R7 e 1 during programming DTACK will negate when the ECAS inputs are negated with AREQ asserted

DTACK will assert from the positive edge of CLK after the ECASs have been asserted

1 0

T If R7 e 0 during programming WAIT will assert when the ECAS inputs are negated with AREQ asserted

WAIT will negate on the negative level of CLK after the ECASs have been asserted

If R7 e 1 during programming DTACK will negate when the ECAS inputs are negated with AREQ asserted

DTACK will assert from the negative level of CLK after the ECASs have been asserted

1 1

0T If R7 e 0 during programming WAIT will assert when the ECAS inputs are negated WAIT will negate when

the ECAS inputs are asserted

If R7 e 1 during programming DTACK will negate when the ECAS inputs are negated DTACK will assert when

the ECAS inputs are asserted

R3 R2

WAIT DTACK Delay Times (See Section 511 or 521)

0 0

NO WAIT STATES If R7 e 0 during programming WAIT will remain high during non-delayed accesses WAIT

will negate when RAS is negated during delayed accesses

NO WAIT STATES If R7 e 1 during programming DTACK will be asserted when RAS is asserted

0 1

T If R7 e 0 during programming WAIT will negate on the negative level of CLK after the access RAS

1T If R7 e 1 during programming DTACK will be asserted on the positive edge of CLK after the access RAS

1 0

NO WAIT STATES

T If R7 e 0 during programming WAIT will remain high during non-delayed accesses

WAIT will negate on the negative level of CLK after the access RAS during delayed accesses

T If R7 e 1 during programming DTACK will be asserted on the negative level of CLK after the access RAS

1 1

1T If R7 e 0 during programming WAIT will negate on the positive edge of CLK after the access RAS

T If R7 e 1 during programming DTACK will be asserted on the negative level of CLK after the positive edge

of CLK after the access RAS

R1 R0

RAS Low and RAS Precharge Time

0 0

RAS asserted during refresh e 2 positive edges of CLK

RAS precharge time e 1 positive edge of CLK

RAS will start from the first positive edge of CLK after GRANTB transitions (DP8432V)

0 1

RAS asserted during refresh e 3 positive edges of CLK

RAS precharge time e 2 positive edges of CLK

RAS will start from the second positive edge of CLK after GRANTB transitions (DP8432V)

1 0

RAS asserted during refresh e 2 positive edges of CLK

RAS precharge time e 2 positive edges of CLK

RAS will start from the first positive edge of CLK after GRANTB transitions (DP8432V)

1 1

RAS asserted during refresh e 4 positive edges of CLK

RAS precharge time e 3 positive edges of CLK

RAS will start from the second positive edge of CLK after GRANTB transitions (DP8432V)

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