DP8430V datasheet(53/56 Pages) NSC

部件名	DP8430V

功能描述	microCMOS Programmable 256k/1M/4M Dynamic RAM Controller/Drivers

PDF	56 Pages

Scroll/Zoom	100%

制造商	NSC [National Semiconductor (TI)]

网页	http://www.national.com

标志

53 / 56 page

130 AC Timing Parameters (Continued)

Unless otherwise stated VCC e 50V g10% 0 C k TA k 70 C the output load capacitance is typical for 4 banks of 18 DRAMs

per bank including trace capacitance (Note 2)

Two different loads are specified

CL e 50 pF loads on all outputs except

CL e 150 pF loads on Q0–8 9 10 and WE or

CH e 50 pF loads on all outputs except

CH e 125 pF loads on RAS0–3 and CAS0–3 and

CH e 380 pF loads on Q0–8 9 10 and WE

Programming

DP8430V31V32V-33

Number

Symbol

Parameter Description

Min

Max

Min

Max

500

tHMLADD

Mode Address Held from ML Negated

501

tSADDML

Mode Address Setup to ML Negated

502

tWML

ML Pulse Width

503

tSADAQML

Mode Address Setup to AREQ Asserted

504

tHADAQML

Mode Address Held from AREQ Asserted

505

tSCSARQ

CS Asserted Setup to

AREQ Asserted

506

tSMLARQ

ML Asserted Setup to AREQ Asserted

TLF11118 – 64

FIGURE 42 500 Programming

DP8430V 数据表(PDF) 53 Page - National Semiconductor (TI)

DP8430V 数据表(HTML) 53 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56

数据表下载