DP8430V datasheet(40/56 Pages) NSC

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130 AC Timing Parameters (Continued)

Unless otherwise stated VCC e 50V g10% 0 C k TA k 70 C the output load capacitance is typical for 4 banks of 18 DRAMs

per bank including trace capacitance (Note 2)

Two different loads are specified

CL e 50 pF loads on all outputs except

CL e 150 pF loads on Q0–8 9 10 and WE or

CH e 50 pF loads on all outputs except

CH e 125 pF loads on RAS0–3 and CAS0–3 and

CH e 380 pF loads on Q0–8 9 10 and WE

Common Parameter

DP8430V31V32V-33

Number

Symbol

Description

Min

Max

Min

Max

1fCLK

CLK Frequency

tCLKP

CLK Period

3 4

tCLKPW

CLK Pulse Width

fDCLK

DELCLK Frequency

tDCLKP

DELCLK Period

7 8

tDCLKPW

DELCLK Pulse Width

tPRASCAS0

RAS Asserted to CAS Asserted

(tRAH e 15 ns tASC e 0 ns)

tPRASCAS1

RAS Asserted to CAS Asserted

(tRAH e 15 ns tASC e 10 ns)

tPRASCAS2

(RAS Asserted to CAS Asserted

(tRAH e 25 ns tASC e 0 ns)

tPRASCAS3

(RAS Asserted to CAS Asserted

(tRAH e 25 ns tASC e 10 ns)

10a

tRAH

Row Address Hold Time (tRAH e 15)

10b

tRAH

Row Address Hold Time (tRAH e 25)

11a

tASC

Column Address Setup Time (tASC e 0)

11b

tASC

Column Address Setup Time (tASC e 10)

tPCKRAS

CLK High to RAS Asserted

following Precharge

tPARQRAS

AREQ Negated to RAS Negated

tPENCL

ECAS0 – 3 Asserted to CAS Asserted

tPENCH

ECAS0 – 3 Negated to CAS Negated

tPARQCAS

AREQ Negated to CAS Negated

tPCLKWH

CLK to WAIT Negated

tPCLKDL0

CLK to DTACK Asserted

(Programmed as DTACK of 12 1 1

or if WAITIN is Asserted)

tPEWL

ECAS Negated to WAIT Asserted

during a Burst Access

tSECK

ECAS Asserted Setup to CLK High to

Recognize the Rising Edge of CLK

during a Burst Access

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