DP8430V datasheet(22/56 Pages) NSC

22 / 56 page

50 Refresh Options (Continued)

In Externally Controlled Refresh the user does not have to

wait for RFRQ to perform a refresh The user can at any

time assert the RFSH input Pulsing RFSH low sets an in-

ternal latch that is used to produce the internal refresh re-

quest The refresh cycle will take place on the next positive

edge of clock as shown in

Figure 15a If an access to the

DRAM is in progress or precharge time for the last access

has not been met the refresh will be delayed Since pulsing

RFSH low sets a latch the user doesn’t have to keep RFSH

low until the refresh starts When the last refresh RAS ne-

gates the internal refresh request latch is cleared

By keeping the input RFSH asserted past the positive edge

of CLK which ends the refresh cycle as shown in

Figure

15b the user will perform another refresh cycle Each re-

fresh cycle during a burst refresh will meet the refresh RAS

low time and the RAS precharge time (programming bits

R0 – 1) This scheme can be thought of as Externally Con-

trolled Burst Refresh If the user desires to burst refresh the

entire DRAM he could generate an end of count signal

(burst refresh finished) by looking at one of the DP8430V

31V32V high address outputs (Q7 Q8 Q9 or Q10) and the

RFIP output The Qn outputs function as a decode of how

many row addresses have been refreshed (Q7 e 128 re-

freshes Q8 e 256 refreshes Q9 e 512 refreshes and Q10

1024 refreshes)

TLF11118 – 23

FIGURE 15a Single Externally Refreshes (2 Periods of RAS Low during Refresh Programmed)

TLF11118 – 24

FIGURE 15b External Burst Refresh

(2 Periods of RAS Precharge 2 Periods of Refresh RAS Low during Refresh Programmed)

DP8430V 数据表(PDF) 22 Page - National Semiconductor (TI)