DP8430V datasheet(33/56 Pages) NSC

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80 Test Mode

Staggered refresh in combination with the error scrubbing

mode places the DP8430V31V32V in test mode In this

mode the 24-bit refresh counter is divided into a 13-bit and

11-bit counter During refreshes both counters are incre-

mented to reduce test time

90 DRAM Critical Timing

Parameters

The two critical timing parameters shown in

Figure 29 that

must be met when controlling the access timing to a DRAM

are the row address hold time tRAH and the column ad-

dress setup time tASC Since the DP8430V31V32V con-

tain a precise internal delay line the values of these param-

eters can be selected at programming time These values

will also increase and decrease if DELCLK varies from

2 MHz

91 PROGRAMMABLE VALUES OF tRAH AND tASC

The DP8430V31V32V allow the values of tRAH and tASC

to be selected at programming time For each parameter

two choices can be selected tRAH the row address hold

time is measured from RAS asserted to the row address

starting to change to the column address The two choices

for tRAH are 15 ns and 25 ns programmable through ad-

dress bit C8

tASC the column address setup time is measured from the

column address valid to CAS asserted The two choices for

tASC are 0 ns and 10 ns programmable through address bit

92 CALCULATION OF tRAH AND tASC

There are two clock inputs to the DP8430V31V32V

These two clocks DELCLK and CLK can either be tied to-

gether to the same clock or be tied to different clocks run-

ning asynchronously at different frequencies

The clock input DELCLK controls the internal delay line

and refresh request clock DELCLK should be a multiple of

2 MHz If DELCLK is not a multiple of 2 MHz tRAH and tASC

will change The new values of tRAH and tASC can be calcu-

lated by the following formulas

If tRAH was programmed to equal 15 ns then tRAH e

15 (((DELCLK Divisor)

2 MHz(DELCLK Frequency))b1)

15 ns

If tRAH was programmed to equal 25 ns then tRAH e

25 (((DELCLK Divisor)

2 MHz(DELCLK Frequency))b1)

25 ns

If tASC was programmed to equal 0 ns then tASC e 125

((DELCLK Divisor)

2 MHz(DELCLK Frequency))

125 ns

If tASC was programmed to equal 10 ns then tASC e 225

((DELCLK Divisor)

2 MHz(DELCLK Frequency))

125 ns

Since the values of tRAH and tASC are increased or de-

creased the time to CAS asserted will also increase or de-

crease These parameters can be adjusted by the following

formula

Delay to CAS e Actual Spec a Actual tRAH b

Programmed tRAH a Actual tASC b Programmed tASC

TLF11118 – 44

FIGURE 29 tRAH and tASC

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