DP8430V datasheet(46/56 Pages) NSC

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130 AC Timing Parameters (Continued)

Unless otherwise stated VCC e 50V g10% 0 C k TA k 70 C the output load capacitance is typical for 4 banks of 18 DRAMs

per bank including trace capacitance (Note 2)

Two different loads are specified

CL e 50 pF loads on all outputs except

CL e 150 pF loads on Q0–8 9 10 and WE or

CH e 50 pF loads on all outputs except

CH e 125 pF loads on RAS0–3 and CAS0–3 and

CH e 380 pF loads on Q0–8 9 10 and WE

Mode 0 Access

DP8430V31V32V-33

Number

Symbol

Parameter Description

Min

Max

Min

Max

300

tSCSCK

CS Asserted to CLK High

301a

tSALECKNL

ALE Asserted Setup to CLK High

Not Using On-Chip Latches or

if Using On-Chip Latches and

B0 B1 Are Constant Only 1 Bank

301b

tSALECKL

ALE Asserted Setup to CLK High

if Using On-Chip Latches if B0 B1

Can Change More Than One Bank

302

tWALE

ALE Pulse Width

303

tSBADDCK

Bank Address Valid Setup to CLK High

304

tSADDCK

Row Column Valid Setup to

CLK High to Guarantee

tASR e 0ns

305

tHASRCB

Row Column Bank Address

Held from ALE Negated

(Using On-Chip Latches)

306

tSRCBAS

Row Column Bank Address

Setup to ALE Negated

(Using On-Chip Latches)

307

tPCKRL

CLK High to RAS Asserted

308a

tPCKCL0

CLK High to CAS Asserted

(tRAH e 15 ns tASC e 0 ns)

308b

tPCKCL1

CLK High to CAS Asserted

(tRAH e 15 ns tASC e 10 ns)

308c

tPCKCL2

CLK High to CAS Asserted

(tRAH e 25 ns tASC e 0 ns)

308d

tPCKCL3

CLK High to CAS Asserted

(tRAH e 25 ns tASC e 10 ns)

309

tHCKALE

ALE Negated Hold from CLK High

310

tSWINCK

WIN Asserted Setup to CLK High

to Guarantee CAS is Delayed

311

tPCSWL

CS Asserted to WAIT Asserted

312

tPCSWH

CS Negated to WAIT Negated

313

tPCLKDL1

CLK High to DTACK Asserted

(Programmed as DTACK0)

314

tPALEWL

ALE Asserted to WAIT Asserted

(CS is Already Asserted)

315

AREQ Negated to CLK High That Starts

Access RAS to Guarantee tASR e 0ns

(Non-Interleaved Mode Only)

316

tPCKCV0

CLK High to Column

Address Valid

(tRAH e 15 ns tASC e 0 ns)

317

tPCKCV1

CLK High to Column

Address Valid

(tRAH e 25 ns tASC e 0 ns)

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DP8430V 数据表(PDF) 46 Page - National Semiconductor (TI)

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