CS8416-CS datasheet(17/48 Pages) CIRRUS

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CS8416

DS578PP2

There are some applications where low jitter in the

recovered clock, presented on the RMCK pin, is

important. For this reason, the PLL has been de-

signed to have good jitter attenuation characteris-

tics. In addition, the PLL has been designed to only

use the preambles of the AES3 or S/PDIF stream to

provide lock update information to the PLL. This

results in the PLL being immune to data dependent

jitter affects because the AES3 or S/PDIF pream-

bles do not vary with the data.

In applications where jitter must be minimized,

special attention should be given to reducing the

noise on the analog power supply and ground for

the PLL filter components. Connecting the filter

components directly to AGND will help decrease

jitter.

The PLL has the ability to lock onto a wide range

of input sample rates with no external component

changes.

5.2.1

OMCK System Clock Mode

A special clock switching mode is available that al-

lows the OMCK clock input to replace RMCK

when the PLL becomes unlocked.

In Software mode this feature is enabled by setting

SWCLK bit in Control1 register to a “1”.

In Hardware Mode this feature is always active.

Clock switching is accomplished without spurious

transitions or glitches on RMCK.

OSCLK and OLRCK are derived from the OMCK

input when the clock has been switched and the se-

rial port is in master mode.

When the PLL loses lock, the frequency of the

VCO drops to ~500 kHz. When this system clock

mode is not enabled, the OSCLK and OLRCK will

be based on the VCO when the PLL is not locked

5.2.2

PLL External Components

The PLL behavior is affected by the external filter

component values. Figure 5 and Figure 6 show the

recommended configuration of the two capacitors

and one resistor required. There are two sets of

component values recommended, depending on the

sample rate of the application. (See Table 2.) The

default set, called “fast”, accommodates input sam-

ple rates of 96 KHz to 192 Hz with no component

changes. It has the highest corner frequency jitter

attenuation curve, and takes the shortest time to

lock. The alternate component set, called “medi-

um” allows the lowest input sample rate to be 32

kHz, and increases the lock time of the PLL. Lock

times are worst case for an Fs transition from un-

locked state to locking to 192 kHz.

It is important to treat the PLL FLT pin as a low

level analog input. It is suggested that the ground

end of the PLL filter be returned directly to the

AGND pin independently of the digital ground

plane.

5.3

Error Reporting and Hold Function

Software Mode

While decoding the incoming AES3 data stream,

the CS8416 can identify several kinds of error, in-

dicated in the Receiver Error register (0Ch).

The errors indicated are:

1) QCRC – CRC error in Q subcode data

2) CCRC – CRC error in channel status data

3) UNLOCK – PLL is not locked to incoming data

stream

4) V – Data Validity bit is set

5) CONF – Input data stream is near error condi-

tion due to jitter degradation

6) BIP – Biphase encoding error

7) PAR – Parity error in incoming data

Range

(kHz)

Rflt

Cflt

Crip

Settling

Time

32 - 192

1 K

Ω

220 nF

10 nF

11ms

medium

96 - 192

3 K

Ω

22 nF

1 nF

4ms

fast

Table 2. External PLL Component Values

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