CS8416-CS datasheet(28/48 Pages) CIRRUS

28 / 48 page

CS8416

DS578PP2

0 - Serial audio output port is in slave mode

1 - Serial audio output port is in master mode

SOSF - OSCLK frequency (for master mode)

Default = ‘0’

0- 64*Fs

1 - 128*Fs

SORES[1:0] - Resolution of the output data on SDOUT

Default = ‘00’

00 - 24-bit resolution

01 - 20-bit resolution

10 - 16-bit resolution

11 - Direct copy of the received NRZ data from the AES3 receiver including C, U, and V bits. The time

slot occupied by the Z bit is used to indicate the location of the block start. This setting forces the

SOJUST bit to be “0”.

SOJUST - Justification of SDOUT data relative to OLRCK

Default = ‘0’

0 - Left-justified

1 - Right-justified (master mode only and SORES

≠11)

SODEL - Delay of SDOUT data relative to OLRCK, for left-justified data formats

(This control is only valid in left justified mode)

Default = ‘0’

0 - MSB of SDOUT data occurs in the first OSCLK period after the OLRCK edge

1 - MSB of SDOUT data occurs in the second OSCLK period after the OLRCK edge

SOSPOL - OSCLK clock polarity

Default = ‘0’

0 - SDOUT sampled on rising edges of OSCLK

1 - SDOUT sampled on falling edges of OSCLK

SOLRPOL - OLRCK clock polarity

Default = ‘0’

0 - SDOUT data is for the left channel when OLRCK is high

1 - SDOUT data is for the right channel when OLRCK is high

CS8416-CS 数据表(PDF) 28 Page - Cirrus Logic