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CS8416-CS 数据表(PDF) 19 Page - Cirrus Logic

部件名 CS8416-CS
功能描述  192 kHZ DIGITAL AUDIO INTERFACE RECEIVER
PDF  48 Pages
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制造商  CIRRUS [Cirrus Logic]
网页  http://www.cirrus.com
标志 CIRRUS - Cirrus Logic

CS8416-CS 数据表(HTML) 19 Page - Cirrus Logic

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CS8416
DS578PP2
19
autodetect software used in Cirrus Logic DSPs. If
the AES3 stream contains sync codes in the proper
format for IEC61937 or DTS data transmission, an
internal AUTODETECT signal will be asserted. If
the sync codes no longer appear after a certain
amount of time, autodetection will time-out and
AUTODETECT will be de-asserted until another
format is detected. In Hardware Mode, the AUDIO
pin is the logical OR of AUTODETECT and the re-
ceived channel status bit 1. In Software mode the
AUDIO pin is available through the GPO pins. Al-
so, the specific data or audio format found by the
autodetect module is available in register 0Bh. Ad-
ditionally, the Pc/Pd burst preambles are available
in registers 23h-26h. If non-audio data is detected,
the data is still processed exactly as if it were nor-
mal audio. The exception is the use of de-emphasis
auto-select feature which will bypass the de-em-
phasis filter if the input stream is detected to be
non-audio. It is up to the user to mute the outputs as
required.
RCBL
out
VLRCK
C, U
Output
RCBL goes high 2 frames after receipt of a Z pre-amble, and is high for 16 frames.
VLRCK is a virtual word clock, available through GPO pins, that can used to frame the C/U ouput.
VLRCK duty cycle is 50%. VLRCK frequency is always equal to the incoming frame rate.
If the serial audio output port is in master mode, VLRCK = OLRCK.
C, U transitions are aligned within 1% of VLRCK period to VLRCK edges
±
Figure 9. C/U data outputs
Figure 10. De-emphasis filter
F2
F1
-10
3.183
Frequency,
KHz
T1 =
50us
0
10.61
Gain,
dB
T2
=15us



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