CS8416

4

DS578PP2

LIST OF FIGURES

Figure 1. Audio Port Master Mode Timing....................................................................................... 7

Figure 2. Audio Port Slave Mode and Data Input Timing ................................................................ 7

Figure 3. SPI Mode Timing.............................................................................................................. 8

Figure 4. I2C Mode Timing.............................................................................................................. 9

Figure 5. Typical Connection Diagram - Software Mode............................................................... 10

Figure 6. Typical Connection Diagram - Hardware Mode ............................................................. 11

Figure 7. AES3 Data Format ......................................................................................................... 14

Figure 8. Serial Audio Output Example Formats........................................................................... 15

Figure 9. C/U data outputs ............................................................................................................ 19

Figure 10. De-emphasis filter ........................................................................................................ 19

Figure 11. Control Port Timing In SPI Mode ................................................................................. 20

Figure 12. Control Port Timing in I2C Mode .................................................................................. 21

Figure 13. Hardware Mode Data Flow .......................................................................................... 37

Figure 14. Professional Input Circuit ............................................................................................. 46

Figure 15. Transformerless Professional Input Circuit .................................................................. 46

Figure 16. Consumer Input Circuit ................................................................................................ 46

Figure 17. S/PDIF MUX Input Circuit ............................................................................................ 46

Figure 18. TTL/CMOS Input Circuit............................................................................................... 46

Figure 19. Channel Status Data Buffer Structure .......................................................................... 47

Figure 20. Flowchart for Reading the E Buffer .............................................................................. 47

LIST OF TABLES

Table 1. Delays by Frequency Values ................................................................................................. 14

Table 2. External PLL Component Values........................................................................................... 17

Table 3. GPO Pin Configurations ........................................................................................................ 22

Table 4. Hardware Mode Serial Audio Format Select ......................................................................... 41