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CS8416-CS 数据表(PDF) 21 Page - Cirrus Logic |
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CS8416-CS 数据表(HTML) 21 Page - Cirrus Logic |
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21 / 48 page ![]() CS8416 DS578PP2 21 read/write bit (R/W) high. The next falling edge of CCLK will clock out the MSB of the addressed register (CDOUT will leave the high impedance state). If the MAP auto increment bit is set to 1, the data for successive registers will appear consecu- tively. The auto increment function is strictly linear. This may result in operations on undefined registers. Reads from undefined registers will produce inde- terminate results. Writing to undefined registers will be ignored. 6.2 I2C Mode In I2C mode, SDA is a bidirectional data line. Data is clocked into and out of the part by the clock, SCL, with the clock to data relationship as shown in Figure 12. There is no CS pin. Each individual CS8416 is given a unique address. Pins AD0 and AD1 form the two least significant bits of the chip address and should be connected to VL+ or DGND as desired. The GPO2 pin is used to set the AD2 bit by connecting a 47K resistor from the GPO2 pin to VL+ or to DGND. The state of the pin is sensed while the CS8416 is being reset. The upper 4 bits of the 7-bit address field are fixed at 0010. To com- municate with a CS8416, the chip address field, which is the first byte sent to the CS8416, should match 0010 followed by the settings of the GPO2, AD1, and AD0. The eighth bit of the address is the R/W bit. If the operation is a write, the next byte is the Memory Address Pointer (MAP) which selects the register to be read or written. If the operation is a read, the contents of the register pointed to by the MAP will be output. Setting the auto increment bit in MAP allows successive reads or writes of con- secutive registers. Each byte is separated by an ac- knowledge bit. The ACK bit is output from the CS8416 after each input byte is read, and is input to the CS8416 from the microcontroller after each transmitted byte. SDA SCL 0010 AD2-0 R/W Start ACK DATA7-0 ACK DATA7-0 ACK Stop Note 2 Note 1 Note 3 Figure 12. Control Port Timing in I2CMode Notes: 1. AD2 is derived from a resistor attached to the GPO2 pin. AD1 and AD0 are determined by the state of the corresponding pins. 2. If operation is a write, this byte contains the Memory Address Pointer, MAP. 3. If operation is a read, the last bit of the read should be NACK (high). |
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