CS8416-CS datasheet(35/48 Pages) CIRRUS

35 / 48 page

CS8416

DS578PP2

9. PIN DESCRIPTION - SOFTWARE MODE

821

RXP3

RXP2

RXP1

RXP0

RXN

VA+

AGND

FILT

RST

RXP4

RXP5

RXP6

RXP7

AD0/CS

OLRCK

OSCLK

SDOUT

OMCK

RMCK

VD+

DGND

VL+

GPO0

GPO1

AD2/GPO2

SDA/CDOUT

SCL/CCLK

AD1/CDIN

RXP[7:0]

RXN

Additional AES3/SPDIF Receiver Port

(Input) - Single-ended receiver inputs carrying AES3 or

S/PDIF digital data. These inputs comprise the 8:2 S/PDIF Input Multiplexer. The select line control is

accessed using the Control 4 register. Please note that any unused inputs can be left floating or tied to

ground. See Appendix A for recommended input circuits.

AES/SPDIF input

- Used along with RXP[X] to form an AES3 differential input. In single-ended

operation this should be capacitively coupled to ground.

VA+

VD+

VL+

Positive Analog Power

- Positive supply for the analog section. Nominally +3.3 V. This supply should

be as quiet as possible since noise on this pin will directly affect the jitter performance of the recovered

clock

Positive Digital Power

– Nominally 3.3 V

Positive – Interface Power

– 3.3 V to 5.0 V: this supply sets the CS8416 I/O levels, including RXPx &

RXN

AGND

DGND

Analog Ground

- Ground for the analog circuitry in the chip. AGND and DGND should be con nected

to a common ground area under the chip.

Digital & I/O Ground

FILT

PLL Loop Filter

(Output) - An RC network should be connected between this pin and analog ground.

For minimum PLL jitter, return the ground end of the filter network directly to AGND

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