CS2000-CP_15 datasheet(9/37 Pages) CIRRUS

部件名	CS2000-CP

功能描述	Fractional-N Clock Synthesizer & Clock Multiplier

PDF	37 Pages

Scroll/Zoom	100%

制造商	CIRRUS [Cirrus Logic]

网页	http://www.cirrus.com

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9 / 37 page

CS2000-CP

DS761F3

PLL PERFORMANCE PLOTS

Test Conditions (unless otherwise specified): VD = 3.3 V; TA =25°C; CL =15pF; fCLK_OUT = 12.288 MHz;

fCLK_IN = 12.288 MHz; Sample size = 10,000 points; Base Band Jitter (100 Hz to 40 kHz); AuxOutSrc[1:0] =11.

100

1,000

10,000

0.1

100

1,000

10,000

Input Jitter Frequency (Hz)

1 Hz Bandwidth

128 Hz Bandwidth

100

1000

10000

-60

-50

-40

-30

-20

-10

Input Jitter Frequency (Hz)

1 Hz Bandwidth

128 Hz Bandwidth

Figure 2. CLK_IN Sinusoidal Jitter Tolerance

Figure 3. CLK_IN Sinusoidal Jitter Transfer

Samples size = 2.5M points; Base Band Jitter (100Hz to 40kHz).

Figure 4. CLK_IN Random Jitter Rejection and Tolerance

0.01

0.1

100

1000

0.01

0.1

100

1000

Input Jitter Level (nsec)

1 Hz Bandwidth

128 Hz Bandwidth

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