CS2000-CP

DS761F3

33

8.9

Function Configuration 3 (Address 1Eh)

8.9.1

Clock Input Bandwidth (ClkIn_BW[2:0])

Sets the minimum loop bandwidth when locked to CLK_IN.

Note:

In order to guarantee that a change in minimum bandwidth takes effect, these bits must be set

prior to acquiring lock (removing and re-applying CLK_IN can provide the unlock condition necessary to

initiate the setting change). In production systems these bits should be configured with the desired values

prior to setting the EnDevCfg bits; this guarantees that the setting takes effect prior to acquiring lock.

76543210

Reserved

ClkIn_BW2

ClkIn_BW1

ClkIn_BW0

Reserved

Reserved

Reserved

Reserved

ClkIn_BW[2:0]

Minimum Loop Bandwidth

000

1 Hz

001

2 Hz

010

4 Hz

011

8 Hz

100

16 Hz

101

32 Hz

110

64 Hz

111

128 Hz

Application:

“Adjusting the Minimum Loop Bandwidth for CLK_IN” on page 17