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CS2000-CP 数据表(PDF) 10 Page - Cirrus Logic

部件名 CS2000-CP
功能描述  Fractional-N Clock Synthesizer & Clock Multiplier
PDF  37 Pages
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制造商  CIRRUS [Cirrus Logic]
网页  http://www.cirrus.com
标志 CIRRUS - Cirrus Logic

CS2000-CP 数据表(HTML) 10 Page - Cirrus Logic

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CS2000-CP
10
DS761F3
CONTROL PORT SWITCHING CHARACTERISTICS- I²C FORMAT
Inputs: Logic 0 = GND; Logic 1 = VD; CL =20pF.
Notes: 13. Data must be held for sufficient time to bridge the transition time, tf, of SCL.
Parameter
Symbol
Min
Max
Unit
SCL Clock Frequency
fscl
-
100
kHz
Bus Free-Time Between Transmissions
tbuf
4.7
-
µs
Start Condition Hold Time (prior to first clock pulse)
thdst
4.0
-
µs
Clock Low Time
tlow
4.7
-
µs
Clock High Time
thigh
4.0
-
µs
Setup Time for Repeated Start Condition
tsust
4.7
-
µs
SDA Hold Time from SCL Falling
(Note 13)thdd
0-
µs
SDA Setup Time to SCL Rising
tsud
250
-
ns
Rise Time of SCL and SDA
tr
-1
µs
Fall Time SCL and SDA
tf
-
300
ns
Setup Time for Stop Condition
tsusp
4.7
-
µs
Acknowledge Delay from SCL Falling
tack
300
1000
ns
Delay from Supply Voltage Stable to Control Port Ready
tdpor
100
-
µs
t buf
t hdst
t hdst
t
low
t r
t f
t
hdd
t high
t sud
t sust
t susp
Stop
Start
Start
Stop
Repeated
SDA
SCL
VD
tdpor
Figure 5. Control Port Timing - I²C Format



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