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CS2000-CP 数据表(PDF) 11 Page - Cirrus Logic

部件名 CS2000-CP
功能描述  Fractional-N Clock Synthesizer & Clock Multiplier
PDF  37 Pages
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制造商  CIRRUS [Cirrus Logic]
网页  http://www.cirrus.com
标志 CIRRUS - Cirrus Logic

CS2000-CP 数据表(HTML) 11 Page - Cirrus Logic

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CS2000-CP
DS761F3
11
CONTROL PORT SWITCHING CHARACTERISTICS - SPI FORMAT
Inputs: Logic 0 = GND; Logic 1 = VD; CL =20pF.
Notes: 14. tspi is only needed before first falling edge of CS after power is applied. tspi = 0 at all other times.
15. Data must be held for sufficient time to bridge the transition time of CCLK.
16. For fcclk < 1 MHz.
Parameter
Symbol
Min
Max
Unit
CCLK Clock Frequency
fccllk
-6
MHz
CCLK Edge to CS Falling
(Note 14)tspi
500
-
ns
CS High Time Between Transmissions
tcsh
1.0
-
µs
CS Falling to CCLK Edge
tcss
20
-
ns
CCLK Low Time
tscl
66
-
ns
CCLK High Time
tsch
66
-
ns
CDIN to CCLK Rising Setup Time
tdsu
40
-
ns
CCLK Rising to DATA Hold Time
(Note 15)tdh
15
-
ns
Rise Time of CCLK and CDIN
(Note 16)tr2
-
100
ns
Fall Time of CCLK and CDIN
(Note 16)tf2
-
100
ns
Delay from Supply Voltage Stable to Control Port Ready
tdpor
100
-
µs
tr2
t f2
t dsu tdh
tsch
tscl
CS
CCLK
CDIN
tcss
tcsh
tspi
tdpor
VD
Figure 6. Control Port Timing - SPI Format (Write Only)



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