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CS2000-CP 数据表(PDF) 16 Page - Cirrus Logic

部件名 CS2000-CP
功能描述  Fractional-N Clock Synthesizer & Clock Multiplier
PDF  37 Pages
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制造商  CIRRUS [Cirrus Logic]
网页  http://www.cirrus.com
标志 CIRRUS - Cirrus Logic

CS2000-CP 数据表(HTML) 16 Page - Cirrus Logic

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CS2000-CP
16
DS761F3
output will resume.
If it is expected that CLK_IN will be removed and then reapplied within 223 SysClk cycles but later than
tCS, the ClkSkipEn bit should be disabled. If it is not disabled, the device will behave as shown in
Figure 14; note that the lower figure shows that the PLL output frequency may change and be incorrect
without an indication of an unlock condition.
Figure 13. CLK_IN removed for > 223 SysClk cycles
CLK_IN
PLL_OUT
UNLOCK
ClkSkipEn=0 or 1
ClkOutUnl=0
Lock Time
CLK_IN
PLL_OUT
UNLOCK
ClkSkipEn=0 or 1
ClkOutUnl=1
Lock Time
= invalid clocks
223 SysClk cycles
223 SysClk cycles
CLK_IN
PLL_OUT
UNLOCK
ClkSkipEn=0 or 1
ClkOutUnl=0
Lock Time
CLK_IN
PLL_OUT
UNLOCK
ClkSkipEn=0 or 1
ClkOutUnl=1
Lock Time
tCS
tCS
= invalid clocks
CLK_IN
PLL_OUT
UNLOCK
ClkSkipEn= 1
ClkOutUnl= 0 or 1
Lock Time
tCS
= invalid clocks
223 SysClk cycles
223 SysClk cycles
223 SysClk cycles
Figure 14. CLK_IN removed for < 223 SysClk cycles but > tCS



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