STLED524 datasheet(10/72 Pages) STMICROELECTRONICS

10 / 72 page

Application schematic

STLED524

10/72

DocID026217 Rev 1

Table 3. Pin description

Name

Description

VBAT1

LDO supply voltage connection(1)

Both VBAT1 and VBAT2 have to be supplied, even though LDO is not used to supply other devices.

VBAT2

Supply voltage connection(1)

B6, B7

Coil connection

VOUT

C6, C7

Step-up converter output voltage

VSUP

LDO output voltage

ROW 0-4

D7, E7, F7, G7,

Matrix row connections

COL 0-23

D4,D5 E1-E6, F1-

F6, G1-G3, G5-

G6, H1-H3, H5-

Matrix column connections

PGND

A6, A7

Power ground

AGND1

Analog ground 1

AGND2

G4, H4

Analog ground 2

GND

Ground

VDD

Logic supply voltage

VIO

I/O pin supply voltage

RESET/PWRDN

Reset input, active low. When low, the device is in

shutdown mode

MISO

Master IN slave OUT (SPI bus)

MOSI

Master OUT slave IN (SPI bus)

Slave select (SPI bus)

SCK

SPU bus clock

CLKIN

Clock input

CLKOUT

Clock output

SYNC

Synchronization input

INT

Interrupt open drain output

LDOGND

Boost output voltage setup resistor connection

ISET

Reference current adjustment resistor connection

TEST

Test input. It has to be connected to GND

STLED524 数据表(PDF) 10 Page - STMicroelectronics

STLED524 数据表(HTML) 10 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72

数据表下载