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STLED524 数据表(PDF) 22 Page - STMicroelectronics |
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STLED524 数据表(HTML) 22 Page - STMicroelectronics |
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22 / 72 page ![]() Detailed description STLED524 22/72 DocID026217 Rev 1 4.5.3 Clock register This register is used to set up clock signals. CLKOUT = 0, CLKOUT pin does not provide any clock signal. It is permanently low CLKOUT = 1, CLKOUT pin provides CLK signal CLKIN = 0, clock signal from the internal oscillator is used for display timings CLKIN = 1, clock signal from CLKIN pin is used for display timings SYNCEN = 0, driver operation synchronization is disabled by an external signal connected to SYNC pin SYNCEN = 1, driver operation synchronization is enabled by an external signal connected to SYNC pin SYNCSEL = 0, driver operation is enabled when SYNC signal is low SYNCSEL = 1, driver operation is enabled when SYNC signal is high REFSEL = 0, external reference defined by RSET value is used for current mirrors REFSEL = 1, internal reference is used for current mirrors If the clock signal changes from internal to external, the external clock has to be provided, at least TINTTOEXTCLK before than CLKIN bit is set to 1. Figure 5. Internal to external clock transition SYNC pin behavior If the synchronization is enabled (SYNCEN = 1), SYNC pin is in inactive state (defined by SYNCSEL bit) and the micro writes EN, DISP or SLPEN bits, but the corresponding operation is delayed, until SYNC pin gets to the active state. If the synchronization is disabled (SYNCEN = 0), the micro writes EN, DISP or SLPEN bits, and the corresponding operation starts immediately. Table 19. Clock register Clock Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Add = 10h - - - REFSEL SYNCSEL SYNCEN CLKIN CLKOUT Default 0 0 0 0 1 0 0 0 NTCLK IEXTCLK (CLKIN pin) CLKIN bit TINTTOEXTLCLK GIPG27021413139LM |
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