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STLED524 数据表(PDF) 14 Page - STMicroelectronics |
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STLED524 数据表(HTML) 14 Page - STMicroelectronics |
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14 / 72 page ![]() Electrical characteristics STLED524 14/72 DocID026217 Rev 1 dCLKOUT Duty cycle of the clock out signal 60 fEXT_MAX Maximum frequency of the external clock signal VIN = 2.7 V to 5.5 V 1.25 MHz dCLKIN Duty cycle of the external clock signal VIN = 2.7 V to 5.5 V 30 70 % TINTTOEXTCLK Transition time from internal to external clock 10 TCLKEX Power switches RDS(on) P-channel on-resistance (boost) 230 m Ω N-channel on-resistance (boost) 130 m Ω RDS(on) P-channel on-resistance (ROW 0 to ROW 4) 500 m Ω N-channel on-resistance (ROW 0 to ROW 4) 200 m Ω RDS(on) Bypass switch on-resistance m Ω ILKG-LX Coil leakage current VIN = VSW2 = 4.0 V 1 µA Time and delay TCLK Clock period 1.667 µs TRTCR Delay between row rising edge and column rising edge 18 TCLK TRTCF Delay between column falling edge and row falling edge 18 TONMIN PWM minimum on-time 2 TONMAX PWM maximum on-time 510 TFRAME Frame period 2560 TROW Row duration 512 Reset TRST Minimum pulse width on RESET pin 100 µs 1. It is strongly recommended to connect VDD pin to VSUP pin directly. 2. It is valid only if LED matrix is not farther than 10 cm from the driver, otherwise ceramic capacitors should be connected between COLx pin and ground to improve ripple. Table 6. Electrical characteristics (continued) Symbol Parameter Test conditions Min. Typ. Max. Unit |
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