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数据搜索系统，热门电子元器件搜索 |
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STLED524 数据表(PDF) 30 Page - STMicroelectronics |
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STLED524 数据表(HTML) 30 Page - STMicroelectronics |
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30 / 72 page  Detailed description STLED524 30/72 DocID026217 Rev 1 A delay and a slope cycle time can be specified for each dot of the matrix separately. The delay is set by PnDLYxx bits, n is a pattern number (see Section 4.4) and xx are the coordinates of a dot. Slope cycle time is set by PnCYCxx bits, n is a pattern number (see Section 4.4) and xx are the coordinates of a dot. PWM duty cycle is incremented / decremented during slope operation in steps stated in Table 32. If the final value of PWM duty cycle given by the value in PWM duty register is not a multiple of the duty cycle step, then last step in phase 1 is truncated to reach the final value of PWM duty cycle given by PWM duty register. Therefore, last step in phase 3 is truncated to reach 0 duty cycle. See Figure 8. Table 33. Delay duration PnDLYxx Delay time 00 No delay 01 1/4 of the slope cycle time 10 1/2 of the slope cycle time 11 3/4 of the slope cycle time Table 34. Slope cycle duration PnCYCxx Cycle time [s] Duration of one phase [s] Duty cycle step 00 0 0 0 01 1.456 0.364 3 10 2.184 0.546 2 11 4.367 1.092 1 |
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