STLED524 datasheet(28/72 Pages) STMICROELECTRONICS

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STLED524

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DocID026217 Rev 1

4.5.12

Latch register

Bits in this register are set when the corresponding interrupt occurs and they are latched.

Those bits, which have been set, can only be cleared by reading the register through SPI.

4.5.13

Status register

Bits in the status register are set and reset according to the state of internal signals

(overtemperature, overvoltage etc.). Reading the status register through SPI does not affect

the state of bits.

BSTOK bit is set to 1 when VOUT voltage has reached the target value. The bit is set to 0, if

VOUT is lower than VOUTSET - VBSTOKHYST. VOUTSET is the target output voltage given by

VOUT[3:0] register. VBSTOKHYST is the hysteresis of BST_OK comparator. An interrupt is

generated, it is enabled and BSTOK bit in the latch register is set.

THP bit is set when thermal protection has been activated (when junction temperature

exceeds TSHDN1). The bit is reset if the temperature falls below TSHDN1HYST thermal

protection hysteresis. An interrupt is generated, when THP bit is set, if it is enabled and THP

bit is set in the latch register. When the thermal protection is activated, EN and BSTEN bits

are set to 0. The device has to be re-enabled through SPI to restart the operation. An

interrupt is also generated when THP bit is reset to 0. So the microcontroller can wait for this

interrupt and then re-enable the device.

OVP bit is set when boost output voltage exceeds VOVP threshold. The bit is reset, if the

voltage falls below the hysteresis of OVP threshold. An interrupt is generated, when this bit

is set, if it is enabled and OVP bit in the latch register is set. The boost is disabled

automatically, BSTEN bit is set to 0.

RSET resistance is checked when EN bit is set to 1. If RSET value is too high (or it is not

connected at all), OPEN bit in the status register is set. An interrupt is generated, if it is

enabled and OPEN bit is set in the latch register.

If RSET value is smaller than RSETMIN (typically 14 kΩ), SHORT bit in the status register is

set to 1. An interrupt is generated, if it is enabled. Current mirrors and boost are not

stopped.

STEP bit is set at the beginning of each scroll step. An interrupt is generated, if it is enabled.

It hasn’t a corresponding bit in the status register.

Table 29. Latch register (read only)

Latch

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Add = 41h

BSTOK ROWSC EOSCR

STEP

SHORT

OPEN

THP

OVP

Default

0000

Table 30. Status register (read only)

Status

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Add = 42h

BSTOK

EOSCR

SHORT

OPEN

THP

OVP

Default

001

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