ENICSF2811PBKA datasheet(105/172 Pages) TI1

105 / 172 page

h(XPLLDIS)

h(XMP/MC)

h(boot-mode)

(C)

, V

(3.3 V)

DDIO

DD3VFL

DDAn

DDAIO

(A)

XCLKIN

2.5 V

XRS

XF/XPLLDIS

XMP/MC

Boot-Mode Pins

, V

[1.8 V (or 1.9 V)]

DD1

XCLKOUT

I/O Pins

User-Code Dependent

Boot-ROM Execution Starts

Peripheral/GPIO Function

Based on Boot Code

GPIO Pins as Input

XPLLDIS Sampling

GPIOF14

GPIO Pins as Input (State Depends on Internal PU/PD)

(Don’t Care)

User-Code Dependent

Address/

Data/

Control

User-Code Execution Phase

XCLKIN/8

(B)

d(EX)

(D)

su(XPLLDIS)

0.3 V

OSCST

w(RSL1)

Address/Data Valid. Internal Boot-ROM Code Execution Phase

TMS320F2810, TMS320F2811, TMS320F2812

TMS320C2810, TMS320C2811, TMS320C2812

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SPRS174T – APRIL 2001 – REVISED MAY 2012

VDDAn – VDDA1/VDDA2 and AVDDREFBG

Upon power up, SYSCLKOUT is XCLKIN/2 if the PLL is enabled. Since both the XTIMCLK and CLKMODE bits in the

XINTCNF2 register come up with a reset state of 1, SYSCLKOUT is further divided by 4 before it appears at

XCLKOUT. This explains why XCLKOUT = XCLKIN/8 during this phase.

After reset, the Boot ROM code executes instructions for 1260 SYSCLKOUT cycles (SYSCLKOUT = XCLKIN/2) and

then samples BOOT Mode pins. Based on the status of the Boot Mode pin, the boot code branches to destination

memory or boot code function in ROM. The BOOT Mode pins should be held high/low for at least 2520 XCLKIN

cycles from boot ROM execution time for proper selection of Boot modes.

If Boot ROM code executes after power-on conditions (in debugger environment), the Boot code execution time is

based on the current SYSCLKOUT speed. The SYSCLKOUT will be based on user environment and could be with or

without PLL enabled.

The state of the GPIO pins is undefined (that is, they could be input or output) until the 1.8-V (or 1.9-V) supply

reaches at least 1 V and 3.3-V supply reaches 2.5 V.

Figure 6-11. Power-on Reset in Microcomputer Mode (XMP/MC = 0) (See Note D)

Electrical Specifications

105

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