ENICSF2811PBKA datasheet(112/172 Pages) TI1

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XCLKOUT

(A)

TDIRx

w(TDIR)

d(PWM)XCO

PWMx

XCLKOUT

(A)

w(PWM)

TMS320F2810, TMS320F2811, TMS320F2812

TMS320C2810, TMS320C2811, TMS320C2812

SPRS174T – APRIL 2001 – REVISED MAY 2012

www.ti.com

6.17 Event Manager Interface

6.17.1 PWM Timing

PWM refers to all PWM outputs on EVA and EVB.

Table 6-18. PWM Switching Characteristics(1)(2)

PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

tw(PWM)

(3)

Pulse duration, PWMx output high/low

Delay time, XCLKOUT high to PWMx

td(PWM)XCO

XCLKOUT = SYSCLKOUT/4

output switching

(1)

See the GPIO output timing for fall/rise times for PWM pins.

(2)

PWM pin toggling frequency is limited by the GPIO output buffer switching frequency (20 MHz).

(3)

PWM outputs may be 100%, 0%, or increments of tc(HCO) with respect to the PWM period.

Table 6-19. Timer and Capture Unit Timing Requirements(1)(2)

MIN

MAX

UNIT

Without input qualifier

2tc(SCO)

tw(TDIR)

Pulse duration, TDIRx low/high

cycles

With input qualifier

1tc(SCO) + IQT

(3)

Without input qualifier

2tc(SCO)

tw(CAP)

Pulse duration, CAPx input low/high

cycles

With input qualifier

1tc(SCO) + IQT

(3)

tw(TCLKINL)

Pulse duration, TCLKINx low as a percentage of TCLKINx cycle time

tw(TCLKINH)

Pulse duration, TCLKINx high as a percentage of TCLKINx cycle time

tc(TCLKIN)

Cycle time, TCLKINx

4tc(HCO)

(1)

The QUALPRD bit field value can range from 0 (no qualification) through 0xFF (510 SYSCLKOUT cycles). The qualification sampling

period is 2n SYSCLKOUT cycles, where “n” is the value stored in the QUALPRD bit field. As an example, when QUALPRD = 1, the

qualification sampling period is 1 × 2 = 2 SYSCLKOUT cycles (that is, the input is sampled every 2 SYSCLKOUT cycles). Six such

samples will be taken over five sampling windows, each window being 2n SYSCLKOUT cycles. For QUALPRD = 1, the minimum width

that is needed is 5 × 2 = 10 SYSCLKOUT cycles. However, since the external signal is driven asynchronously, a 11-SYSCLKOUT-wide

pulse ensures reliable recognition.

(2)

Maximum input frequency to the QEP = min[HSPCLK/2, 20 MHz]

(3)

Input Qualification Time (IQT) = [tc(SCO) × 2 × QUALPRD] × 5 + [tc(SCO) × 2 × QUALPRD].

XCLKOUT = SYSCLKOUT

Figure 6-18. PWM Output Timing

XCLKOUT = SYSCLKOUT

Figure 6-19. TDIRx Timing

112

Electrical Specifications

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