ENICSF2811PBKA datasheet(116/172 Pages) TI1

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GPIO

Signal

Sampling Window

Output

From Qualifier

SYSCLKOUT

QUALPRD = 1

(SYSCLKOUT/2)

See Note (A)

Sampling period, determined by GPxQUAL

[QUALPRD]

(SYSCLKOUT cycle x 2 x QUALPRD) x 5

TMS320F2810, TMS320F2811, TMS320F2812

TMS320C2810, TMS320C2811, TMS320C2812

SPRS174T – APRIL 2001 – REVISED MAY 2012

www.ti.com

6.19 General-Purpose Input/Output (GPIO) – Input Timing

This glitch is ignored by the input qualifier. The QUALPRD bit field specifies the qualification sampling period. It can

vary from 00 to 0xFF. Input qualification is not applicable when QUALPRD = 00. For any other value “n”, the

qualification sampling period is 2n SYSCLKOUT cycles (that is, at every 2n SYSCLKOUT cycle, the GPIO pin will be

sampled). Six consecutive samples must be of the same value for a given input to be recognized.

For the qualifier to detect the change, the input must be stable for 10 SYSCLKOUT cycles or greater. In other words,

the inputs should be stable for (5 × QUALPRD × 2) SYSCLKOUT cycles. This would enable five sampling periods for

detection to occur. Since external signals are driven asynchronously, a 13-SYSCLKOUT-wide pulse provides reliable

recognition.

Figure 6-24. GPIO Input Qualifier – Example Diagram for QUALPRD = 1

116

Electrical Specifications

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Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812

ENICSF2811PBKA 数据表(PDF) 116 Page - Texas Instruments