ENICSF2811PBKA datasheet(119/172 Pages) TI1

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SPISOMI

SPISIMO

SPICLK

(clock polarity = 1)

SPICLK

(clock polarity = 0)

Master In Data

Must Be Valid

Master Out Data Is Valid

SPISTE

(A)

TMS320F2810, TMS320F2811, TMS320F2812

TMS320C2810, TMS320C2811, TMS320C2812

www.ti.com

SPRS174T – APRIL 2001 – REVISED MAY 2012

In the master mode, SPISTE goes active 0.5tc(SPC) before valid SPI clock edge. On the trailing end of the word, the SPISTE will go inactive 0.5tc(SPC) after the receiving

edge (SPICLK) of the last data bit, except that SPISTE stays active between back-to-back transmit words in both FIFO and non-FIFO modes.

Figure 6-26. SPI Master Mode External Timing (Clock Phase = 0)

Electrical Specifications

119

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Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812

ENICSF2811PBKA 数据表(PDF) 119 Page - Texas Instruments

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