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ENICSF2811PBKA 数据表(PDF) 120 Page - Texas Instruments

部件名 ENICSF2811PBKA
功能描述  Digital Signal Processors
PDF  172 Pages
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制造商  TI1 [Texas Instruments]
网页  http://www.ti.com
标志 TI1 - Texas Instruments

ENICSF2811PBKA 数据表(HTML) 120 Page - Texas Instruments

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TMS320F2810, TMS320F2811, TMS320F2812
TMS320C2810, TMS320C2811, TMS320C2812
SPRS174T – APRIL 2001 – REVISED MAY 2012
www.ti.com
Table 6-27. SPI Master Mode External Timing (Clock Phase = 1)(1)(2)
SPI WHEN (SPIBRR + 1) IS EVEN OR
SPI WHEN (SPIBRR + 1) IS ODD AND
SPIBRR = 0 OR 2
SPIBRR > 3
NO.
UNIT
MIN
MAX
MIN
MAX
1
tc(SPC)M
Cycle time, SPICLK
4tc(LCO)
128tc(LCO)
5tc(LCO)
127tc(LCO)
ns
tw(SPCH)M
Pulse duration, SPICLK high
0.5tc(SPC)M – 10
0.5tc(SPC)M
0.5tc(SPC)M – 0.5tc(LCO) – 10
0.5tc(SPC)M – 0.5tc(LCO)
(clock polarity = 0)
2(3)
ns
tw(SPCL)M
Pulse duration, SPICLK low
0.5tc(SPC)M – 10
0.5tc(SPC)M
0.5tc(SPC)M – 0.5tc(LCO) – 10
0.5tc(SPC)M – 0.5tc(LCO)
(clock polarity = 1)
tw(SPCL)M
Pulse duration, SPICLK low
0.5tc(SPC)M – 10
0.5tc(SPC)M
0.5tc(SPC)M + 0.5tc(LCO) – 10
0.5tc(SPC)M + 0.5tc(LCO)
(clock polarity = 0)
3(3)
ns
tw(SPCH)M
Pulse duration, SPICLK high
0.5tc(SPC)M – 10
0.5tc(SPC)M
0.5tc(SPC)M + 0.5tc(LCO) – 10
0.5tc(SPC)M + 0.5tc(LCO)
(clock polarity = 1)
tsu(SIMO-SPCH)M
Setup time, SPISIMO data valid
0.5tc(SPC)M – 10
0.5tc(SPC)M – 10
before SPICLK high
(clock polarity = 0)
6(3)
ns
tsu(SIMO-SPCL)M
Setup time, SPISIMO data valid
0.5tc(SPC)M – 10
0.5tc(SPC)M – 10
before SPICLK low
(clock polarity = 1)
tv(SPCH-SIMO)M
Valid time, SPISIMO data valid after
0.5tc(SPC)M – 10
0.5tc(SPC)M – 10
SPICLK high (clock polarity = 0)
7(3)
ns
tv(SPCL-SIMO)M
Valid time, SPISIMO data valid after
0.5tc(SPC)M – 10
0.5tc(SPC)M – 10
SPICLK low (clock polarity = 1)
tsu(SOMI-SPCH)M
Setup time, SPISOMI before
0
0
SPICLK high (clock polarity = 0)
10(3)
ns
tsu(SOMI-SPCL)M
Setup time, SPISOMI before
0
0
SPICLK low (clock polarity = 1)
tv(SPCH-SOMI)M
Valid time, SPISOMI data valid after
0.25tc(SPC)M – 10
0.5tc(SPC)M – 10
SPICLK high (clock polarity = 0)
11(3)
ns
tv(SPCL-SOMI)M
Valid time, SPISOMI data valid after
0.25tc(SPC)M – 10
0.5tc(SPC)M – 10
SPICLK low (clock polarity = 1)
(1)
The MASTER/SLAVE bit (SPICTL.2) is set and the CLOCK PHASE bit (SPICTL.3) is set.
(2)
tc(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR + 1)
tc(LCO) = LSPCLK cycle time
(3)
The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).
NOTE: Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate:
•
Master mode transmit: 20 MHz MAX. Master mode receive: 12.5 MHz MAX.
•
Slave mode transmit: 12.5 MHz MAX. Slave mode receive: 12.5 MHz MAX.
120
Electrical Specifications
Copyright © 2001–2012, Texas Instruments Incorporated
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Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812



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