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ENICSF2811PBKA 数据表(PDF) 118 Page - Texas Instruments |
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ENICSF2811PBKA 数据表(HTML) 118 Page - Texas Instruments |
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118 / 172 page  TMS320F2810, TMS320F2811, TMS320F2812 TMS320C2810, TMS320C2811, TMS320C2812 SPRS174T – APRIL 2001 – REVISED MAY 2012 www.ti.com Table 6-26. SPI Master Mode External Timing (Clock Phase = 0)(1)(2) SPI WHEN (SPIBRR + 1) IS EVEN OR SPI WHEN (SPIBRR + 1) IS ODD AND SPIBRR = 0 OR 2 SPIBRR > 3 NO. UNIT MIN MAX MIN MAX 1 tc(SPC)M Cycle time, SPICLK 4tc(LCO) 128tc(LCO) 5tc(LCO) 127tc(LCO) ns tw(SPCH)M Pulse duration, SPICLK high 0.5tc(SPC)M – 10 0.5tc(SPC)M 0.5tc(SPC)M – 0.5tc(LCO) – 10 0.5tc(SPC)M – 0.5tc(LCO) (clock polarity = 0) 2(3) ns tw(SPCL)M Pulse duration, SPICLK low 0.5tc(SPC)M – 10 0.5tc(SPC)M 0.5tc(SPC)M – 0.5tc(LCO) – 10 0.5tc(SPC)M – 0.5tc(LCO) (clock polarity = 1) tw(SPCL)M Pulse duration, SPICLK low 0.5tc(SPC)M – 10 0.5tc(SPC)M 0.5tc(SPC)M + 0.5tc(LCO) – 10 0.5tc(SPC)M + 0.5tc(LCO) (clock polarity = 0) 3(3) ns tw(SPCH)M Pulse duration, SPICLK high 0.5tc(SPC)M – 10 0.5tc(SPC)M 0.5tc(SPC)M + 0.5tc(LCO) – 10 0.5tc(SPC)M + 0.5tc(LCO) (clock polarity = 1) td(SPCH-SIMO)M Delay time, SPICLK high to SPISIMO –10 10 –10 10 valid (clock polarity = 0) 4(3) ns td(SPCL-SIMO)M Delay time, SPICLK low to SPISIMO –10 10 –10 10 valid (clock polarity = 1) tv(SPCL-SIMO)M Valid time, SPISIMO data valid after 0.5tc(SPC)M – 10 0.5tc(SPC)M + 0.5tc(LCO) – 10 SPICLK low (clock polarity = 0) 5(3) ns tv(SPCH-SIMO)M Valid time, SPISIMO data valid after 0.5tc(SPC)M – 10 0.5tc(SPC)M + 0.5tc(LCO) – 10 SPICLK high (clock polarity = 1) tsu(SOMI-SPCL)M Setup time, SPISOMI before SPICLK 0 0 low (clock polarity = 0) 8(3) ns tsu(SOMI-SPCH)M Setup time, SPISOMI before SPICLK 0 0 high (clock polarity = 1) tv(SPCL-SOMI)M Valid time, SPISOMI data valid after 0.25tc(SPC)M – 10 0.5tc(SPC)M – 0.5tc(LCO) – 10 SPICLK low (clock polarity = 0) 9(3) ns tv(SPCH-SOMI)M Valid time, SPISOMI data valid after 0.25tc(SPC)M – 10 0.5tc(SPC)M – 0.5tc(LCO) – 10 SPICLK high (clock polarity = 1) (1) The MASTER/SLAVE bit (SPICTL.2) is set and the CLOCK PHASE bit (SPICTL.3) is cleared. (2) tc(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR + 1) tc(LCO) = LSPCLK cycle time (3) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6). NOTE: Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate: • Master mode transmit: 20 MHz MAX. Master mode receive: 12.5 MHz MAX. • Slave mode transmit: 12.5 MHz MAX. Slave mode receive: 12.5 MHz MAX. 118 Electrical Specifications Copyright © 2001–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812 |
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