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ENICSF2811PBKA 数据表(PDF) 123 Page - Texas Instruments

部件名 ENICSF2811PBKA
功能描述  Digital Signal Processors
PDF  172 Pages
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制造商  TI1 [Texas Instruments]
网页  http://www.ti.com
标志 TI1 - Texas Instruments

ENICSF2811PBKA 数据表(HTML) 123 Page - Texas Instruments

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20
15
SPISIMO
SPISOMI
SPICLK
(clock polarity = 1)
SPICLK
(clock polarity = 0)
SPISIMO Data
Must Be Valid
SPISOMI Data Is Valid
SPISTE
(A)
12
13
14
16
19
TMS320F2810, TMS320F2811, TMS320F2812
TMS320C2810, TMS320C2811, TMS320C2812
www.ti.com
SPRS174T – APRIL 2001 – REVISED MAY 2012
A.
In the slave mode, the SPISTE signal should be asserted low at least 0.5tc(SPC) before the valid SPI clock edge and
remain low for at least 0.5tc(SPC) after the receiving edge (SPICLK) of the last data bit.
Figure 6-28. SPI Slave Mode External Timing (Clock Phase = 0)
Copyright © 2001–2012, Texas Instruments Incorporated
Electrical Specifications
123
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Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812



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