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ENICSF2811PBKA 数据表(PDF) 126 Page - Texas Instruments |
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ENICSF2811PBKA 数据表(HTML) 126 Page - Texas Instruments |
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126 / 172 page  TMS320F2810, TMS320F2811, TMS320F2812 TMS320C2810, TMS320C2811, TMS320C2812 SPRS174T – APRIL 2001 – REVISED MAY 2012 www.ti.com 6.22 External Interface (XINTF) Timing Each XINTF access consists of three parts: Lead, Active, and Trail. The user configures the Lead/Active/Trail wait states in the XTIMING registers. There is one XTIMING register for each XINTF zone. Table 6-30 shows the relationship between the parameters configured in the XTIMING register and the duration of the pulse in terms of XTIMCLK cycles. Table 6-30. Relationship Between Parameters Configured in XTIMING and Duration of Pulse(1)(2) DURATION (ns) DESCRIPTION X2TIMING = 0 X2TIMING = 1 LR Lead period, read access XRDLEAD × tc(XTIM) (XRDLEAD × 2) × tc(XTIM) AR Active period, read access (XRDACTIVE + WS + 1) × tc(XTIM) (XRDACTIVE × 2 + WS + 1) × tc(XTIM) TR Trail period, read access XRDTRAIL × tc(XTIM) (XRDTRAIL × 2) × tc(XTIM) LW Lead period, write access XWRLEAD × tc(XTIM) (XWRLEAD × 2) × tc(XTIM) AW Active period, write access (XWRACTIVE + WS + 1) × tc(XTIM) (XWRACTIVE × 2 + WS + 1) × tc(XTIM) TW Trail period, write access XWRTRAIL × tc(XTIM) (XWRTRAIL × 2) × tc(XTIM) (1) tc(XTIM) – Cycle time, XTIMCLK (2) WS refers to the number of wait states inserted by hardware when using XREADY. If the zone is configured to ignore XREADY (USEREADY = 0), then WS = 0. Minimum wait state requirements must be met when configuring each zone’s XTIMING register. These requirements are in addition to any timing requirements as specified by that device’s data sheet. No internal device hardware is included to detect illegal settings. ● If the XREADY signal is ignored (USEREADY = 0), then: 1. Lead: LR ≥ tc(XTIM) LW ≥ tc(XTIM) These requirements result in the following XTIMING register configuration restrictions (no hardware to detect illegal XTIMING configurations): XRDLEAD XRDACTIVE XRDTRAIL XWRLEAD XWRACTIVE XWRTRAIL X2TIMING ≥ 1 ≥ 0 ≥ 0 ≥ 1 ≥ 0 ≥ 0 0, 1 Examples of valid and invalid timing when not sampling XREADY (no hardware to detect illegal XTIMING configurations): XRDLEAD XRDACTIVE XRDTRAIL XWRLEAD XWRACTIVE XWRTRAIL X2TIMING Invalid 0 0 0 0 0 0 0, 1 Valid 1 0 0 1 0 0 0, 1 126 Electrical Specifications Copyright © 2001–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812 |
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