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ENICSF2811PBKA 数据表(PDF) 128 Page - Texas Instruments |
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ENICSF2811PBKA 数据表(HTML) 128 Page - Texas Instruments |
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128 / 172 page  TMS320F2810, TMS320F2811, TMS320F2812 TMS320C2810, TMS320C2811, TMS320C2812 SPRS174T – APRIL 2001 – REVISED MAY 2012 www.ti.com ● If the XREADY signal is sampled in the asynchronous mode (USEREADY = 1, READYMODE = 1), then: 1. Lead: LR ≥ tc(XTIM) LW ≥ tc(XTIM) 2. Active: AR ≥ 2 × tc(XTIM) AW ≥ 2 × tc(XTIM) NOTE: Restriction does not include external hardware wait states 3. Lead + Active: LR + AR ≥ 4 × tc(XTIM) LW + AW ≥ 4 × tc(XTIM) NOTE: Restriction does not include external hardware wait states These requirements result in the following XTIMING register configuration restrictions (no hardware to detect illegal XTIMING configurations): XRDLEAD XRDACTIVE XRDTRAIL XWRLEAD XWRACTIVE XWRTRAIL X2TIMING ≥ 1 ≥ 2 0 ≥ 1 ≥ 2 0 0, 1 or (no hardware to detect illegal XTIMING configurations): XRDLEAD XRDACTIVE XRDTRAIL XWRLEAD XWRACTIVE XWRTRAIL X2TIMING ≥ 2 ≥ 1 0 ≥ 2 ≥ 1 0 0, 1 Examples of valid and invalid timing when using asynchronous XREADY (no hardware to detect illegal XTIMING configurations): XRDLEAD XRDACTIVE XRDTRAIL XWRLEAD XWRACTIVE XWRTRAIL X2TIMING Invalid 0 0 0 0 0 0 0, 1 Invalid 1 0 0 1 0 0 0, 1 Invalid 1 1 0 1 1 0 0 Valid 1 1 0 1 1 0 1 Valid 1 2 0 1 2 0 0, 1 Valid 2 1 0 2 1 0 0, 1 128 Electrical Specifications Copyright © 2001–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812 |
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